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Adaptive Deep Brain Stimulation (aDBS) has been proposed in literature to avoid the negative consequences associated with the continuous stimulation delivered through traditional deep brain stimulation. This work seeks to determine a group of neural biomarkers that a classification algorithm could use on an aDBS device using rodent animal models. The neural activities were acquired from the primary motor cortex of four Parkinsonian model rats and four healthy rats from a control group. To overcome the variability introduced from the small rat sample size, this work proposes a novel method for combining and running Genetic Feature Selection and Forward Stepwise Feature Selection in an environment where classification accuracy varies greatly based on how the folds are organized before cross-validation. Three separate classification algorithms, Logistic Regression, k-Nearest Neighbor, and Random Forest are used to verify the proposed method. For Logistic Regression, the set of Alpha Power (7-12 Hz), High Beta Power (20-30 Hz), and 55-95 Hz Gamma Power shows the best performance in classification. For k-Nearest Neighbor, the characterizing features are Low Beta Power (12-20 Hz), High Beta Power, All Beta Power (12-30 Hz), 55-95 Hz Gamma Power, and 95-105 Hz Gamma Power. For Random Forest, they are High Beta Power, All Beta Power, 55-95 Hz Gamma Power, 95-105 Hz Gamma Power, and 300-350 Hz High-Frequency Oscillations Power. With the selected feature set, experimental results show an increasing classification accuracy from 59.08% to 77.69% for Logistic Regression, from 49.53% to 73.44% for k-Nearest Neighbor, and from 54.10% to 71.15% for Random Forest. Clinical Relevance- This experiment provides a method for determining the most effective biomarkers from a larger set for classifying Parkinsonian behavior for an aDBS device.

Image based motion tracking of human skeletons is widely used in biomechanical research, while electromyography (EMG) contains direct reflections of the muscle activities. A combination of image and EMG data enables a more effective way to quantitatively evaluate the recover level of patients with movement disorders, such as post-stroke patients. This paper proposed a wireless multiple-mode human behavior evaluation system enables simultaneously acquisition of multiple image sensor data and acquisition of EMG data from different muscles. Several wireless wearable EMG sensor nodes are attached to different muscles-of-interest over the body. Each EMG sensor node features an individual acquisition channel. The collected data are transferred through Bluetooth Low Energy. Each EMG node features a size of 2cm × 3cm × 1cm with a weight of 16 gram and a battery life of 20 hours. Two Wi-Fi based wireless image sensors are used. A convolutional neural network based human pose estimation method is proposed to track the skeleton motion features from the captured streams. The fully wireless nature guarantees the usability and flexibility of the proposed system. A data collection and remote analysis platform is also developed for remote support. The proposed system has been tested on patients recovering from stroke.

This paper proposed an epilepsy seizure detection ASIC design using only one channel EEG signal as input. The proposed design consists of 10 sub-bands FIR filters and band energy feature extraction engines. A MAC is utilized as a linear SVM classifier. The design was fabricated in TSMC 180nm technology with a power consumption of 3.09 µJ/Classification. According to experimental results, the average sensitivity is reduced by less than 10% while the area is reduced by 70%. With patient-specific configurable parameters, a higher than 90% dection sensitivity was achieved on half of the patients in the testing dataset.

This session covers biomedical systems with innovations that traverse device, circuit, and system-level design. The first paper describes a retinal prosthetic that utilizes an optically-addressed nanowire array in conjunction with a transmitter-offloaded wireless neural stimulation approach for efficient operation near sensitive retinal tissue. A pneumatic-free fully-CMOS-controlled microfluidics platform for label-free cellular and bio-molecular sensing comes next, followed by a CMOS microscopic-scale thermal actuation and sensing array for localized heating of magnetic nanoparticles for hyperthermia cancer therapy. The final paper showcases a wireless multimode IC integrating electrochemical sensors, a temperature sensor, and a current stimulator for monitoring chronic wound healing processes.

In this work, a wireless compact general-purpose electrochemical biosensor system was designed for continuous health index monitoring in implantable and/or wearable devices. Two different modes, the SCAN mode and the COLLECT mode, are applied in the proposed design. During the SCAN mode, the redox potential is optimized to improve the robustness of the COLLECT mode by enabling a relatively high amplitude of the output current design. The total weight is 4.5 gram including a 0.5Wh Li-battery, which can be applied to freely-moving small animal subjects for over 24-hour. The Experimental results shows a linearity of 0.9997, and a sensitivity of 2nA. Nitric oxide and Nitrite are used to demonstrate the concentration of the proposed system. In-vivo experiment was applied in the joint cavity of the New Zealand white rabbit.

This paper presents a power efficient 12-bit successive aproximation register analog-to-digital converter (SAR ADC) operated at a supply voltage of 0.6V. A binary-scaled redundant technology for SAR ADC is proposed based on split-capacitor DAC architecture. It suppresses the decision error without sacrificing the resolution. In addition, a feedback controlled bias technique is applied to the comparator reducing the power consumption for comparison by 21.6%. The proposed ADC was fabricated in 0.18μm CMOS technology, occupiing an core area of 0.07mm2. The measured DNL and INL is +0.46/−0.50 LSB and +0.98/−0.95 LSB, respectively. A SINAD of 68.1dB and SFDR of 83.0dB are achieved, respectively, while operating at a sampling rate of 100kS/s. The power consuming of the proposed ADC is 1.35uW, resulting in an FOM of 6.5fJ/Conversion-step.

The difference in EEG data among subjects and sessions is an essential factor affecting the accuracy in neural signal analysis. This paper proposed a Tri-FeatureNet, an adversarial learning-based feature extraction algorithm to learn representations invariant to subjects and sessions for sleep staging. The proposed work improves the algorithm's robustness to individual differences. The invariant features are combined with the subject-specified features and the temporal features to further compensate for the loss of sleep information during adversarial training. The proposed model makes use of the temporal information in EEG signals and sleep staging sequences at the same time. This is the first time that adversarial training was proposed to extract the task-related features for different subjects and different sessions in sleep staging. The proposed algorithm was implemented in a portable sleep staging system. Experimental results illustrated an 82.9% ACC in sleep staging task with a single-channel EEG signal.

Intelligent tracking of the behavior information of animal subject is important in multiple mode brain-machine-interface implementation in neuroscience research. This work proposes a low latency, low computation complexity image-based tracking system with a wireless neural interface. The proposed tracker integrated a light scale feature points recognition network and a prediction module for real-time location tracking. A detector is used to initialize the location of the target animal as well as to fix the error generated from the tracker. Experimental results shows a state-of-the-art processing rate of 117fps based on 2.4GHz, 20 cores CPU resources and a 166fps based on a GPU server resources.

This paper presents a 427MHz OOK modulated transmitter with energy harvesting for multi-channel neural acquisition. A power efficient OOK modulator is proposed integrated a 3-input AND gate array to drive the power transistors. The requirement on the driving capability of the VCO output is greatly reduced. A 9-stage ring oscillator based VCO is designed with PLL and edge-combining technology. A crystal based 6.78MHz oscillator is combined with the wireless power transmitter coil to power up the entire transmitter design, as well as to generate a reference frequency to the transmitter, resulting a crystal-less transmitter design. The proposed design was fabricated in 180nm technology, occupying a silicon area of only 0.26mm2. Experimental results show a power consumption of $96\mu \mathbf{W}$ with a -19dBm output. A 48pJ/bit efficiency is achieved under a data rate of 2Mbps.

A biphasic current-matching neural stimulator based on $\mathbf{0.18\ \mu m}$ CMOS process is presented. The stimulator can output biphasic current ranging from $\mathbf{5\ \mu A}$ to $\mathbf{160\ \mu A}$ and its stimulation pulse width can be adjusted from $\mathbf{17\ \mu s}$ to $\mathbf{250\ \mu s}$ . The proposed stimulator consists of a bandgap reference, a digital block for stimulus width control, the high-matching current drivers to produce adjustable biphasic current, and an on-chip voltage buffer. In order to achieve biphasic current matching, feedback loop is built in the circuit design to keep each current highly stabilized. The stimulation result demonstrates that this system can realize biphasic well-matched stimulation current. The error of the current matching is within 1.76%.

Closed-loop bidirectional Sensor-Brain-Machine Interface (SBMI) systems with wireless communication capability have shown significant value in neuroscience studies recently. However, most rack-mount medical instrumentation currently used in neuroscience research labs only allow experiments in tethered or sedated animals. Customized miniature wireless SBMI devices, which operate reliably on freely behaving animals, are highly desirable. The design of such system places significant challenges in both circuit and system level. This paper analyzes the system requirements and discusses the design strategies, followed by an example of a fully integrated wireless SBMI for augmenting perception. The design paradigm presented in this work can be used in extensive range of neuroscience studies in unrestrained animals.

This paper proposes a chopper amplifier working under 0.8V supply voltage implemented in TSMC 0.18um CMOS technology, enabling a 2.02uW per channel, while preserving a good tolerance of power-line interference (PLI) up to 600mV pp , a THD of -65.5dB, and high robustness against the PVT, by implementing a common-mode cancellation loop (CMCL) based on a feedback loop, a new offset cancellation loop (OCL), and a new very-lower transconductance (VLT) OTA. The measured mid-band gain is 43.3dB with a high-pass cut-off of 1.2Hz and a low-pass cut-off of 17kHz. The measured integrated noise is 0.75uVrms and 4.8uVrms in the frequency band of 1 − 200Hz and 0.2 − 17kHz, respectively, leading to a power efficiency factor (PEF) of 8.4 and 4.05.

This paper proposed the design of a general purpose, wireless, wearable, multiple channel neural stimulator design. The proposed design enables wireless configuration through a Bluetooth communication link. The proposed stimulator features a weight of 10g and a volume size of 30mm x 25mm x 10mm. Rechargeable battery is used in the proposed stimulator. An iOS based Graphic User Interface (GUI) is designed for the remote configuration as well as monitoring of the status. An image sensor based motion tracker is designed and implemented in FPGA to track the location of the target animal subject in real-time. A central controller is designed to communicate to all the functional modules.

An exponential current generation circuit for neural stimulators is presented. Compared to the conventional exponential current generation circuits, the proposed circuit features higher bandwidth and a smaller error of 2.34%. The output of the proposed exponential current generation circuit ranges from 1.16 to 75.36 $\mu A$. This circuit is designed in a 180-nm CMOS technology under 1.8-V supply voltage.

This paper proposed an attention evaluation system using 8-channel differential prefrontal EEG signals acquired from the forehead. A 16-channel neural signal acquisition module was designed and fabricated in TSMC 180nm CMOS process. It consists of chopper LNAs, switched-Capacitor programmable gain amplifiers and 12-bit SAR ADC. The proposed digital attention evaluation algorithm was implemented on FPGA, including IIR filters, calculation of the filtered neural signal strength indicator, SVM-based classifier.

This paper presents the design of a low-noise chopper amplifier for neural signal acquisition in the presence of the in-band stimulation artifacts that exist in the closed-loop neuromodulation system. In order to avoid saturation due to the artifacts, the gain of the amplifier is designed to be 26dB. A modified positive feedback loop is introduced to boost both inband and DC input impedance. The Gm-C integrator without external capacitors is used in the DC-Servo-Loop (DSL) to filter out the electrode offset. To further enhance the linearity, the voltage divider technique is employed at the input of the Gm-C integrator. The proposed work was fabricated using a 0.18um CMOS process. The amplifier consumes 3.42μW under 1.8V supply voltage, while occupying an area of 0.219mm2. The measured input-referred noise is 1.12μVrms (1 Hz–200 Hz) and 4.65μVrms (200 Hz-5 kHz). A DC input impedance of 90MΩ, a CMRR of 103dB, and a PSRR of 78dB are achieved as well.

This paper proposed the design of a low noise chopper amplifier with low total harmonic distortion (THD) for neural signal acquisition. A Gm-C integrator based DC-servo-loop (DSL) with complementary input and elaborate bias scheme was integrated in the proposed work to improve the linearity and noise performance, which is dominated by DSL of the chopper amplifier in low frequency band. The proposed amplifier was fabricated in TSMC 0.18um CMOS process, occupying an area of 0.2mm2, featuring a power consumption of 3.24μW/channel under 1.8V supply voltage. The THD for a 5mV pp input is lower than −60dB. An input-referred thermal noise PSD of 39 nV/√Hz is measured. The measured input-referred noise is 0.65μV rms in the 0.3Hz-200Hz frequency band and 2.14μV rms in 200Hz-5kHz, respectively. In addition, the high-pass corner frequency can be precisely configured and linearly adjusted with the external bias current from 0.35Hz to 54.5Hz.

This paper proposed a design of a closed-loop, bi-directional brain-machine-interface (BMI). The proposed chip consists of 16-channel neural acquisition, 8-channel neural stimulation, action potential detection, feature extraction and support vector machine (SVM) for spike sorting. A closed-loop control strategy is utilized to trigger different stimulation pattern according to different detected spike categories. The 16-channel neural signal acquisition is comprised of 16-channel low noise amplifier (LNA) which shares a single Programmable Gain Amplifier (PGA) draws a total current of 218uA under a power supply of 3.3V. Arbitrary combination is realized for the stimulator channel control. The frequency, the output current amplitude, the pulse width and the burst number are all tunable. The first and second derivative extrema method is applied to the detected action potential before spike sorting, realizing a great reduction on the data to be processed in the SVM. A single two-class sorting module is implemented as a results from the tradeoff between area and latency. More than two-class spike sorting is realized by a repeating of the two-class sorting procedure. The design has been fabricated in TSMC 180nm HV COMS process, occupying a silicon area of 5mm × 2mm.

This paper proposed the architecture of a linear current-mode CMOS image sensor integrated parallel processing unit enabling various block-level calculation during the read-out procedure. Combinational logic with two scanning DFF chains and global control signals as input generates the output to address the right pixels with high flexibility. Four current conveyors are used to perform CDS function for the chosen pixels. Four digitally programmable scaling units and a TIA based arithmetic unit are integrated for the proposed computation procedure. The 240×200 image sensor was fabricated in 0.18um standard 4T CIS technology with a pixel size of 9um×9um and a fill factor of 30%. One computation operation can be done within 3us with a power consumption of 309uW in average for analog circuits.

Brain-machine interface (BMI) is one of the most important tools in the neuroscience research and neuroprosthetics development. The investigation and development of BMI have achieved significant progress in the past decade. However, several bottlenecks from the electrical engineering perspective still have to be overcome. The next generation BMI system would feature bi-directional neural interface with on-chip neural feature extraction and machine learning. Moreover, the high integration, compact packing and wireless operation would allow the experiments in freely behaving animals. This paper reviews the state-of-the-art designs, summarizes the key design requirements and challenges in a BMI system, and provides insights in both circuit and system level design.

This paper presents a fully integrated wireless sensor brain machine interface system to restore continuous somatosensory feedback from the hand. A wireless bi-directional neural interface system-on-chip (SoC) and a wireless sensor node design are described in this work. The neural interface integrates a 16-channel neural recording front-end, a 16-channel electrical stimulation back-end, a successive approximation analog-to-digital converter (ADC), a custom digital controller, and an ultra-wide band (UWB) wireless transceiver. The sensor node features a custom designed optical force sensor, a low-power level-crossing ADC, an UWB transmitter, and analog interface to off-chip accelerometers. The optical force sensor is developed in standard CMOS with low-cost post fabrication. Multiple sensor nodes can be used to trigger pre-defined microstimulation in different brain areas for restoring finger sensation. The prototypes have been fabricated in 180nm standard CMOS technology. Bench testing and In-Vivo experimental results are presented in this paper. The system was designed to investigate the first chronic interface to the cuneate nucleus of macaques, and showed a promising solution for sensation restoration in future neuroprosthetics.

This paper presents a novel neuroprosthetic system for perception encoding. The system consists of a wireless waterproof bi-directional neural interface and an object tracking image sensor. The neural interface features a fully programmable 8-channel neural stimulator, a compliance voltage and impedance monitoring module, a 16-channel neural recording front-end, and a duplex wireless transceiver. The image sensor features a 180×180 pixel array, with in-pixel comparator for energy efficient color thresholding based object detection tracking. A unique experiment was designed in which rats navigate a water maze using only brain stimulation to inform their location relative to a hidden platform. Custom hardware and software have been developed to support the investigation, with special attention paid to the safety of the animals during the experiment. The proposed chip designs have been fabricated in 180nm CMOS technology. This work demonstrates a novel experimental paradigm, and that the developed wireless neuroprosthetic system can be used to conduct extensive sensory encoding experiments in freely behaving animals.

Brain-Machine-Interface (BMI) is a system that builds artificial pathways between different parts of the neural system. Due to different application scenarios, a BMI system may consist of a neural signal acquisition, electrical neural stimulation, signal processing, wireless communication, and power management. This paper reviews the state-of-art development in system-on-a-chip BMI design technology from application to circuit design details. A perspective on the future trend is also included.

The sense of touch and proprioception are critical to movement control. After spinal cord injury, these senses may be restored with direct, electrical microstimulation of the brain as part of a complete sensorimotor neuroprosthesis. The present study was designed to test, in part, the hypothesis that the cuneate nucleus (CN) of the brainstem is a suitable site to encode somatosensory information. Two rhesus macaques were implanted with microelectrode arrays providing chronic access to the CN. The monkeys were trained on an active touch oddity task to detect vibrotactile stimuli. When the vibrotactile stimuli were replaced with electrical stimuli delivered to the CN, initial detection probabilities were near chance. Detection performance improved over time, reaching a plateau after about 10 daily sessions. At plateau performance, the monkeys exhibited detection probabilities that were 68-80% higher than the chance probability. Finally, detection probability was quantified as a function of stimulus amplitude. The resulting psychometric curve showed a detection threshold of 45 μA for 100-Hz stimulus trains. These behavioral data are the first to show that artificial CN activation is sufficient for perception. The results are consistent with our hypothesis and motivate future tests of the CN as a somatosensory encoding site.

This paper presents a bidirectional neural interface, consisting of 12-channel low-noise amplifiers, channel-level neural feature extraction and proportional-integral-derivative (PID) controller, voltage and current mode analog-to-digital converters (ADC), and 12-channel multi-mode stimulators. The neural amplifier features a wide-band from 0.5Hz to 10kHz with a noise floor of 3.02μVrms. The input stage has been designed for high stimulation voltage tolerance, and fast stimulation artifact recovery. The digitally assisted, analog parallel feature extraction processor features an ultra low power consumption while performing 1) neural signal energy extraction in programmable frequency band and time window, or 2) action potential detection using a current-mode time-amplitude window discriminator. A programmable PID controller has been implemented at the channel-level for closed-loop operation. A 640nW 8-bit current-mode ADC featuring a FoM of 10.7fJ/conv-step at a sampling rate of 250kSps has been designed for action potential digitization, and a voltage-mode SAR ADC with a ENOB of 9.1 and FoM of 34.2fJ/conv-step has been implemented for neural features and local field potential digitizations. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4mA and a compliance voltage up to +/-5V in arbitrary channel configuration. The chip has been fabricated in 0.18μm HV-CMOS technology, occupying a silicon area of 2.2 mm2. The whole chip dissipates 276μW on average. Bench testing, in-vitro and in-vivo experimental results are presented in this paper.

This paper presents a 12-channel, low-power, high efficiency neural signal acquisition front-end for local field potential and action potential signals recording. The proposed neural front-end integrates low noise instrumentation amplifiers, low-power filter stages with configurable gain and cut-off frequencies, a successive approximation register (SAR) ADC, and a realtime compressed sensing processing unit. A capacitor coupled instrumentation amplifier integrated input impedance boosting has been designed, dissipating 1μA quiescent current. An input referred noise of 1.63μV was measured in the frequency band of 1Hz to 7kHz. The noise efficiency factor (NEF) of the amplifier is 0.76. The SAR ADC achieves an ENOB of 10.6-bit at a sampling rate of 1MS/s. A compressed sensing processing unit with configurable compression ratio, up to 8x, was integrated in the design. The design has been fabricated in 180nm CMOS, occupying 4.5mm×1.5mm silicon area. A portable neural recorder has been built with the custom IC and a commercial low-power wireless module. A 4.6g lithium battery supports the device for a continuous compressed sensing recording up to 70 hours.

In this paper, a wireless electrogoniometer is described using a pair of ultra-wide band (UWB) wireless smart sensor nodes that are interfaced to low power 3-axis accelerometers. A high resolution SAR ADC as well as a low power asynchronous continuous sampling event-driven ADC are integrated for the digitization of the input signal under different operation modes. An anti-self-locking circuit is included in the asynchronous event-driven ADC to improve the robustness. A tri-channel UWB transceiver is designed particularly for the data transmission of the 3-axis accelerometers. A power consumption of 4.6pJ/bit is achieved for the transmitter at 10Mbps while operating under 1.2V power supply. The receiver power consumption can be as low as 0.32nJ/bit at 10Mbps under 1.8V supply. To demonstrate one application of the device, the electrogoniometer was used to quantify the in-vivo response of a somatosensory neuron to joint angle changes.

CMOS Polarization image sensors can detect the polarization of an incident light, from which a lot of information can be derived about the properties and shape of the images objects. This paper proposes a current mode polarization analyzer, based on a three-parameter polarization analysis methodology. The procedure of the calculation of the intensity, polarization degree, and the polarization angle is optimized in a format for hardware friendly implementation. The proposed analysis procedure is implemented using only absolute adder/subtractors and multiplier/dividers. In this work, the multiplier/divider is performed in two modes: i) geometric mean calculation mode, and ii) square/divider mode. Both a parallel implementation, which employs five multiplier/divider, for the optimization of processing efficiency, and a serial implementation, which employs two multiplier/divider, for the optimization of power efficiency, are designed and compared. A prototype chip of the proposed design was implemented in 0.5μm 3M2P standard CMOS technology, occupying a silicon area of 150 × 140 μm 2 .

A voltage controlled MEMS oscillator (VCMO) fabricated in 65nm CMOS process is proposed in this paper. The piezoelectric aluminum nitride (AlN) Contour-Mode MEMS resonator based oscillator can be operated under multiple frequencies from 204MHz, to 517MHz, to 850MHz. A maximum overall tuning range of 611ppm is achieved at a center frequency of 204MHz. The proposed oscillator operates in the sub-threshold region, resulting in a power consumption of 47μW measured under a 0.55V power supply, which is the lowest reported in literature for an application in the 200MHz range. The measured oscillator phase noise is -77dBc/Hz at 1kHz offset from the 204MHz carrier.

In this paper, we propose a novel low power multimode CMOS smart image sensor node with integrated focal-plane motion detection and video compression. An 80×80 image pixel array is fabricated in 0.5 μm 3M2P standard CMOS technology, occupying 3×3 mm2 silicon area. The proposed imager enables various operational modes, including 1) event generator mode, 2) motion tracking mode and 3) video output mode in full-resolution or compression by region of interest (ROI). An ultra low power focal-plane motion detection block, consisting of analog memory and dual-threshold comparator, is integrated in the pixel-level circuit for on-chip motion detection. A hardware-friendly motion tracking algorithm is developed that indicates ROIs according to a strategy based on the detection results. A 12-bit on-chip, off-array ADC is employed to convert the captured light intensity into digital readouts. In order to further reduce the power consumption, lower image resolution is used under the first two modes. A trade-off analysis between the image resolution and detection accuracy is proposed in this paper. In simulation, the total power consumption is 10μW at a frame rate of 30fps and a supply voltage of 3.3V in motion tracking mode. A compression ratio of 14% and an average PSNR of 42dB is achieved in compressive video output mode.

Current mode image sensors enable an easy implementation of focal plane algebraic functions, but suffer from poor linearity performance. A theoretical analysis is first performed on the source of the non-linearity for current mode image sensors. According to the analysis, an architecture of a current mode image sensor with a voltage feedback loop between pixel output and the current conveyor for linearity enhancement is proposed. An image sensor array of 100 × 200 current mode pixels is fabricated in 0.5um 2P3M standard CMOS processing technology. Experimental results illustrate a 45% improvement of the linearity of the proposed imager. Fixed pattern noise is reduced by 19% at the saturation level and signal to noise ratio of 49.6dB is achieved.

Some animals, such as crustaceans, arthropods, insects and aquatic creatures can detect a characteristic of light - polarization, that is invisible to humans. Different approaches of polarization imaging in the visual region have been proposed in the literature that employ precise but bulky optical devices. In recent years, taking advantage of nano-fabrication, researchers began integrating polarization films at the focal plane of standard image sensors. In addition, the development of nano-scale CMOS technology enables the integration of a standard pixel array with metallic wire-grid at the scale of the wavelength of visible light. Monolithic wire-grid polarization image sensor designs have been reported in the last few years, which is promising to be employed as a compact, portable, smart polarization detection device to extend the human visual ability.

Polarization is one of the important characteristics of visible light that can not be detected by human visual system or traditional image sensors. In this paper, we report on an image sensor integrated focal plane 2 × 2 wire-grid polarizer filter mosaic targeted at visible spectrum fabricated in 65nm standard CMOS processing line, which enables the reconstruction of the polarization response characteristic for each pixel. Finite-Difference Time-Domain method has been used for the first time to optimize the extinction ratio in visible spectrum of the multilayer focal plane wire-grid polarizer. Experimental results show that an extinction ratio around 10 is achieved with a standard error of around 0.25% between the experimental results and the fitting sinusoidal polarization response curve. A phase error at the level of less than 2% to the measurement phase resolution is achieved. These results are the best reported for a monolithic wire-grid polarization image sensor design for visible spectrum.

In this paper, architecture of a three dimensional (3D) compressive acquisition CMOS image sensor integrated with on-line parallel compression algorithm is proposed. The proposed 3D sensor architecture consists of three hierarchy layers: an image acquisition hierarchy, an image compression hierarchy layer, and an image storage hierarchy layer. The image acquisition hierarchy converts light intensity into current using photodiode. In the second layer, the analog current values are converted into time-slot by comparing with a reference voltage value. The time-slot signal is used in the on-line compression processing. The digital brightest pixel value is used as a reference value, while the differential value between the reference and the raw pixel value is calculated and quantized. The quantized results (typically 2-bit) as well as the reference brightest pixel value are stored in the third hierarchy layer. Compared with standard two dimensional (2D) compressive acquisition CMOS image sensor design, about 70% silicon area is reduced by the 3D integration of different layers. In addition, the increase of the fill factor can be expected as high as near 100%.

In this paper, a block-based online compressive sampling scheme for digital pixel sensor (DPS) is proposed. The overall sensor array is divided into blocks whereby one randomly selected pixel within each block is sampled using a random access control circuit. The latter is performed using off-array horizontal and vertical control logic. The random access addresses are updated during readout phase using low complexity logic operations performed on the readout pixel values. A sparse matrix, consisting of all the sampled pixel values, is buildup to reconstruct the image by solving the l 1 -norm minimization as the linear programming problem in the framework of Convex Optimization. The proposed system features reduced on-chip compression processing complexity and significant reduced memory requirement. System level simulation results show that a 25dB reconstructed image quality in terms of PSNR is achieved enabling a compression ratio of 4. In addition, a pixel-level memory requirement reduction of 75% is achieved when compared to a standard PWM DPS architecture.

In this paper, the architecture of a digital pixel sensor (DPS) array with an online 1-bit predictive coding algorithm using Hilbert scanning scheme is proposed. The architecture of the sensor array reduces by more than half the silicon area of the DPS by sampling and storing the differential values between the pixel and its prediction, featuring compressed dynamic range and hence requiring limited precision (only 1-bit signed value in the proposed architecture as compared to 8-bit unsigned full precision). Hilbert scanning is used to read-out the pixel's value, hence avoiding discontinuity in the read-out path, which is shown to improve the quality of the reconstructed image. The Hilbert scanning path is all carried out by hardware wire connection without increasing the circuit complexity of the sensor array. Reset pixels are inserted into scanning path to overcome the error accumulation problem inherent in predictive coding. System level simulation results show a PSNR of around 25dB can be reached while using the proposed 1-bit Hilbert predictive coding algorithm. VLSI implementation results illustrate a pixel level implementation featuring a pixel size reduction of 67% with a fill-factor of 40% compared with a standard PWM DPS architecture.

In this paper, we propose a compact block-based compressive acquisition CMOS image sensors. The overall image is decomposed into blocks. The proposed design reorders the raw captured pixel values within each block, only recording the brightest pixel value and the darkest pixel value for each block using full precision (typically 8-bit). During reconstruction, block models are built to model the value distribution within one block. As in a digital pixel sensor (DPS) array the pixel data are naturally ordered (from the brightest to the darkest pixel), the block-level hardware overload while implementing the proposed scheme is very low. The proposed scheme enables reduced memory requirement, and hence enabling significant silicon area saving. The compression performance and image quality of the proposed algorithm are thoroughly analyzed for different block sizes and a mathematical model is subsequently derived. Simulation result shows that the proposed algorithm enables more than 80% pixel-level memory reduction at a PSNR level around 23dB and using 1BPP.

In this paper, an online differential compression algorithm with reset columns integrated along with a digital pixel sensor (DPS) array is proposed. The proposed architecture of the sensor array reduces by more than half the silicon area of the DPS by sampling and storing the differential values between the pixel and its prediction, featuring compressed dynamic range and hence requiring limited precision (typically 2-3 bits as compared to 8-bit full precision). Column based reset technique is proposed to overcome the error accumulation problem inherent in predictive coding. While the concept of predictive coding was extensively introduced in previous literature, this is the first time this concept is used to reduce the storage requirement at the pixel level and hence drastically improving both the pixel size and the fill-factor - a key problem in DPS implementation. System level simulation results show the importance of the proposed reset scheme while VLSI implementation results illustrate a pixel level implementation of the whole predictive coding scheme featuring a pixel size reduction of more than 40% with a fill-factor of more than 15%.

This paper proposes a low power full-custom CMOS digital pixel sensor array designed for a wireless endoscopy capsule. The proposed architecture greatly reduces the on-chip memory requirement by sharing pixel-level memory in the sensor array with the digital image processor. The pixel-level memories in the proposed full-custom image sensor are used not only to store the raw image pixel values in the image capture phase, but also is also used as buffers for the digital image processor during the image compression and transmission phase. Low power design is carried out both at the algorithmic and circuit levels, which reduces almost 50% switching activities on data bus, about 80% of power consumption in the main pixel circuit during image capture phase and 15% during image process phase while transmitting data at a rate of 2-frame/s.

In this paper, a block-based architecture of digital pixel sensor (DPS) array integrated with an on-line compression algorithm is proposed. The proposed technique is based on a block divided storage and compression scheme of the original image. Image capture, storage, and reordering are completed simultaneously and performed on-line while storing pixel value into the on-chip memory array. More than 60% of memory saving is achieved using the proposed block-based design. Furthermore, block-based design greatly reduces the accumulation error inherent in DPCM type of processing. Simulation results show that the PSNR result can reach around 30 dB with a compression ratio of less than 3 BPP.