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With 3D stacking design, high-performance low-power complex design is practical. However, due to the high design costs and extensive design efforts, 3D technology is not broadly adopted. For 3D stacking designs, most chip failures are due to power supply problems of voltage drop and noisy voltage. A feasible low-cost 3D stacking design method is proposed. Multiple voltage design technique is applied to reduce power consumption. A low-power built-in digitalized power-aware management mechanism for multiple voltage domain design is adopted. A power switch control circuit is used to support multiple operation modes for multiple voltage designs. A built-in voltage meter is proposed for internal voltage level observation. A powerless retention flip flop is applied for temporary data storage. These efficient power-aware adjusting mechanisms are successfully validated by a low-power, noisy-voltage tolerant 64bit multiplier using a low-cost 3D stacking technique.