19 results on '"Miwa, Shinobu"'
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2. Functionally-Predefined Kernel: a Way to Reduce CNN Computation
3. Multi-Level Packet Processing Caches
4. Data Prediction for Response Flows in Packet Processing Cache
5. Evaluation of Task Mapping on Multicore Neural Network Accelerators
6. Initial Study of Reconfigurable Neural Network Accelerators
7. Low-power cache memory with state-of-the-art STT-MRAM for high-performance processors
8. Runtime multi-optimizations for energy efficient on-chip interconnections1
9. Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches
10. Data-aware power management for periodic real-time systems with non-volatile memory
11. Normally-off computing project: Challenges and opportunities
12. Integrating Multi-GPU Execution in an OpenACC Compiler
13. Performance modeling for designing NoC-based multiprocessors
14. Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping
15. Predict-More Router: A Low Latency NoC Router with More Route Predictions
16. Communication Library to Overlap Computation and Communication for OpenCL Application
17. Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating
18. Parallelizing Hilbert-Huang Transform on a GPU
19. McRouter: Multicast within a router for high performance network-on-chips.
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