Search

AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay (TCRIT). The UDL can be used in any product without any need for customizing. In addition, averaging the results of distributed 4 monitors with a pitch of 3 mm in a chip can reduce errors due to within-die variation by half. With these techniques, proposed scheme produces equivalent or less error to TCRIT than does a conventional scheme that uses a single critical path replica as a delay monitor, even with simple monitor design. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%. [ABSTRACT FROM PUBLISHER]

A small-size on-chip transformer-based digital isolator for power control systems is proposed. With a proposed pulse generation and detection scheme that enables a 5 V standard CMOS transistor to utilize GHz-band signals, transformer area is reduced to 1/4–1/8 that of conventional transformers. A test chip achieves a 2.5 kV isolation voltage, a 35 kV/us CMR, a 1.6 mA static current and a 250 Mbps data rate, all which are equal to or superior to those of optocouplers or conventional digital isolators. The developed technology greatly reduces the number of chips in power control systems by allowing integration of multiple isolators in a CMOS chip together with microcontrollers or gate drivers. Moreover, the high-speed low-power capability expands the application potential to include isolated serial links, controller area network (CAN), FlexRay, medical devices, displays, sensors, etc. [ABSTRACT FROM PUBLISHER]

A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 \mu\ m \times \,100 \mu\ m). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution. [ABSTRACT FROM PUBLISHER]

A 27-Mbps, frequency-division multiplexing (FDM) receiver was developed. The 3-channel FDM signal is demodulated in the receiver with a traveling subband demodulator using intrasymbol intermittent demodulation for each subband, which does not require an analog-to-digital converter/fast Fourier transform. Also, the receiver sustains a sensitivity of -55 dBm comparable to that of, e.g., Bluetooth standards (-70 dBm) with respect to 14-dB sensitivity degradation caused by signal bandwidth enhancement, with receiver power dissipation of 3 mW. Furthermore, we have successfully demonstrated energy-exploitation capability from the power of unused FDM signals and interference. [ABSTRACT FROM AUTHOR]

A dynamic-reconfigurable memory chip is fabricated, by which on-chip memories of an SoC chip can be moved to the memory chip to increase the efficiency of memory usage, and stacked on a logic chip by using three dimensional packaging technology. In the memory chip, many RAM-macros are arrayed and they are connected through two dimensional mesh network interconnects. By using memory-specified network interconnects, area overhead of network interconnects for the memory chip is reduced by 63% and the latency overhead by 43%. Signal lines between the two chips are directly connected by 10-pm-pitch inter-chip electrodes, resulting in fast and low-energy inter-chip transmission. [ABSTRACT FROM AUTHOR]

A 2.0 Gb/s clock-embedded interface for LCD drivers, Advanced-PPmL™, has been developed for high-speed data transfer and reduced area in transmission media. Only one pair of differential signals is needed to control the LCD driver and to display images. A newly developed 1/5-rate phase frequency detector helps achieve a 25% power reduction compared with a half-rate architecture. Pulse filtering of phase control signals and a 4B5B-based interface protocol have been developed for noise-tolerant clock recovery. Power consumption in the clock and data recovery (CDR) is 93 mW with a 3.0 V supply. The rms jitter in the recovered clock is 11 ps when a PRBS7 pattern is used. [ABSTRACT FROM AUTHOR]

We describe a cost-effective and low-power-consumption approach for on-chip optical interconnection. This approach includes an investigation into architectures, devices, and materials. We have proposed and fabricated a bonded structure of an Si-based optical layer on a large-scale integration (LSI) chip. The fabricated optical layer contains Si nanophotodiodes for optical detectors, which are coupled with SiON waveguides using surface-plasmon antennas. Optical signals were introduced to the optical layer and distributed to the Si nanophotodiodes. The output signals from the photodiodes were sent electrically to the transimpedance-amplifier circuitries in the LSI. The signals from the photodiodes triggered of the circuitries at 5 GHz. Since electrooptical modulators consume the most power in on-chip optical interconnect systems and require a large footprint, they are critical to establish on-chip optical interconnection. Two approaches are investigated: 1) an architecture using a fewer number of modulators and 2) high electrooptical coefficient materials. [ABSTRACT FROM AUTHOR]

Our RF signal-quality measurement macro employs 1) a new window-shifting measurement technique that obtains the power of a high-frequency component on the basis of lower-frequency measurements, and 2) a new stair-like weighted addition technique that decreases error due to harmonic power, phase, and DC offset in measured signals. The macro occupies only 1/10 the area of conventional on-chip spectrum analyzers. Carrier power for 2.4 GHz-Tx was successfully measured with digital testers alone, with an error of only <1 dB, and harmonic-emission exceeding FCC regulations (>-20 dBm) was also successfully detected. [ABSTRACT FROM AUTHOR]

This paper reports the development of an in-field real- time successive jitter-measurement macro whose features include i-ps resolution jitter measurement. The newly developed jitter-measurement macro has four key features: 1) interpolated jitter oversampling; 2) a hierarchical Vernier delay line; and 3) feedforward calibration, each of which helps attain high jitter-measurement resolution; as well as 4) an oversampling rate and measurement range-control technique. A test chip of the macro has been fabricated in a 90-nm process. It successfully measures small random jitter with 1-ps resolution, and large deterministic jitter can also be measured by extending the jitter-measurement range by a factor of 4. [ABSTRACT FROM AUTHOR]

A linear bias-independent gate capacitor (BIGCAP) with large intrinsic capacitance and low parasitic capacitance is proposed. BIGCAP is composed of a pair of accumulation-mode n-poly gate capacitors in an n-well and a pair of pMOS gate capacitors, which requires no additional fabrication process steps. Measured results with 1.5-V 0.13-µm digital CMOS technology show that the intrinsic capacitance is 6.7 fF/µm² (6.7 times bigger than that of typical MIM capacitors) and the parasitic capacitance is 1.9% of the intrinsic capacitance (1/5 that of typical MIM capacitors). The linearity is ±2.9% and capacitance variation across a wafer is as small as σ = 0.096%. For a 0.1-V threshold voltage variation, the capacitance variation was only σ = 0.69% and the linearity ranged from ±2.84% to ±2.93%. For three types of BIGCAP using 1.5-V, 2.5-V, and 3.3-V MOSFETs, less than ±4% linearity is achievable by optimizing the ratio (x) of the pMOS gate capacitors' area to the area of the n-poly gate capacitors, and the optimum x value is within a range of 15%-25%. BIGCAP has been applied to the loop filter of a differential phase-locked loop (PLL) and reduces the gate area of the largest loop filter capacitor to only 35% of that of the conventional design while achieving reasonable jitter of 7.0 ps (rms) and 74.4 ps (peak-to-peak) at 840 MHz with a 1.5-V supply. [ABSTRACT FROM AUTHOR]

In this paper, a reconfigurable LSI employing a non- volatile nanometer-scale switch, NanoBridge, is proposed, and its basic operations are demonstrated. The switch, composed of solid electrolyte copper sulfide, has a <30-nm contact diameter and <100-Ω on-resistance. Because of its small size, it can be used to create extremely dense field-programmable logic arrays. A 4 × 4 crossbar switch and a 2-input look-up-table circuit are fabricated with 0.18-µm CMOS technology, and operational tests with them have confirmed the switch's potential for use in programmable logic arrays. A 1-kb nonvolatile memory is also presented, and its potential for use as a low-voltage memory device is demonstrated. [ABSTRACT FROM AUTHOR]

Introduces an equalization that can handle frequency-dependent attenuation. Problems of conventional equalization; Introduction of a post-equalization combining technique; Presentation of a continuous-time post-equalization.

The article introduces a special issue of papers from the 2009 Symposium on VLSI Circuits held at the Rihga Royal Hotel in Kyoto, Japan from June 16-18, 2009, which include topics on Very Large Scale Integration (VLSI) designers and improvements in VLSI circuit design.

The article presents the editors' introduction on the special issue of the "IEEE Journal of Solid-State Circuits," which features papers from the 2008 Symposium on very large-scale integrated (VLSI) Circuits held on June 18-20 at the Hilton Hawaiian Village in Honolulu, Hawaii.