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69 results on '"Namba, Kazuteru"'

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12. L band circularly polarized SAR onboard microsatellite

13. Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM).

15. On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction.

18. Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems.

24. Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems.

25. A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories.

26. High-Speed Parallel Decodable Nonbinary Single-Error Correcting (SEC) Codes.

41. Parallel Decodable Two-Level Unequal Burst Error Correcting Codes.

42. Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM).

43. A Single and Adjacent Symbol Error-Correcting Parallel Decoder for Reed–Solomon Codes.

46. Design of a Nonvolatile 7T1R SRAM Cell for Instant-on Operation.

47. A Single-Bit and Double-Adjacent Error Correcting Parallel Decoder for Multiple-Bit Error Correcting BCH Codes.

48. Concurrent Error Detection of Binary and Nonbinary OLS Parallel Decoders.

49. An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.

50. Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing.

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