Search

Neuromorphic computing is an emerging research field that aims to develop new intelligent systems by integrating theories and technologies from multiple disciplines, such as neuroscience, deep learning and microelectronics. Various software frameworks have been developed for related fields, but an efficient framework dedicated to spike-based computing models and algorithms is lacking. In this work, we present a Python-based spiking neural network (SNN) simulation and training framework, named SPAIC, that aims to support brain-inspired model and algorithm research integrated with features from both deep learning and neuroscience. To integrate different methodologies from multiple disciplines and balance flexibility and efficiency, SPAIC is designed with a neuroscience-style frontend and a deep learning-based backend. Various types of examples are provided to demonstrate the wide usability of the framework, including neural circuit simulation, deep SNN learning and neuromorphic applications. As a user-friendly, flexible, and high-performance software tool, it will help accelerate the rapid growth and wide applicability of neuromorphic computing methodologies. [ABSTRACT FROM AUTHOR]

Reservoir computing (RC) is a neural computing paradigm especially well-suited for learning dynamical systems by leveraging an untrained reservoir layer, providing high-dimensional input encoding with fading memory property. Since only the readout weights are trained under RC, linear regression learning algorithms are sufficient, leading to significant improvements in computational complexity and energy efficiency as compared to other deep neural networks (DNNs). RC offers an alternative solution to sidestep the shortcomings of data scarcity and the vanishing gradient problem. More importantly, such a network structure is amenable to hardware implementation using a variety of devices, circuits, and systems, making RC a good candidate to replace sophisticated DNNs as a lightweight classifier at the edge for internet of things (IoT) applications. In this article, we provide an overview of recent advances in RC hardware and their applications for mobile edge intelligence. Specifically, we will demonstrate the design strategies of RC in opto-electronic configuration, fully digital system, and silicon with the mixed-signal integrated circuit approach. Moreover, we will expose a novel implementation approach using emerging materials, designing the way for RC to be used in the next-generation neuromorphic computing systems. Building upon these efficient RC models, their applicability and effectiveness against the state-of-the-art are then demonstrated through diverse machine learning benchmarks spanning the area of IoT, communication networks, and healthcare. [ABSTRACT FROM AUTHOR]

This work highlights the utilization of the floating body effect and charge-trapping/de-trapping phenomenon of a Silicon-nanowire (Si-nanowire) charge-trapping memory for an artificial synapse of neuromorphic computing application. Charge trapping/de-trapping in the nitride layer characterizes the long-term potentiation (LTP)/depression (LTD). The accumulation of holes in the potential well achieves short-term potentiation (STP) and controls the transition from STP to LTP. Also, the transition from STP to LTP is analyzed through gate length scaling and high-κ material (Al2O3) for blocking oxide. Furthermore, the conductance values of the device are utilized for system-level simulation. System-level hardware parameters of a convolutional neural network (CNN) for inference applications are evaluated and compared to a static random-access memory (SRAM) device and charge-trapping memory. The results confirm that the Si-nanowire transistor with better gate controllability has a high retention time for LTP states, consumes low power, and archives better accuracy (91.27%). These results make the device suitable for low-power neuromorphic applications. [ABSTRACT FROM AUTHOR]

Lithium (Li)-ion materials such as LiCoO2 and (Li3PO4)-N (LiPON) are used in Li-ion all-solid-state batteries, and are now expected to be used as ion-electron hybrid materials to create a new degree of freedom in future integrated circuits. We fabricated thin-film devices on the basis of LiCoO2/LiPON/Cu and ultrathin titanium oxide ( ${\mathrm {TiO}}_{x}$ ) to demonstrate their new type of resistance change mechanism and characteristics. Multi-level resistance changes promising as synaptic plasticity were obtained, and the resistance properties enable neuromorphic computing to enter a new era.

Linear weights modulation in neuromorphic memristor plays an important role in high-accuracy image recognition task. Herein, a Li+ doped organic artificial memristor for neuromorphic computing was proposed for linear weights update, which shows active ions diffusive dynamics as Ca2+ diffusion in biological synapse. The memristor exhibits gradual resistive switching, multi-state storage and typical synaptic behaviors. In addition, the synaptic learning capability of letter “T” was demonstrated in a memristors array. By designing consecutive pulse waveforms with enhanced amplitude, the linearity of memristor for weight update in long-term potentiation and depression (LTP/LTD) could be improved from 6.8 to 0.4. Based on the great nonlinearity factor in LTP ($\alpha _{\text {p}}={1.5}$) and LTD ($\alpha _{\text {d}}={0.4}$), face recognition was achieved with high accuracy of 96% by artificial neural network consisting of ion doped memristors. The ion doped organic memristor with highly linear weights update provides guidelines for the development of bio-inspired ion diffusive neuromorphic computing system. [ABSTRACT FROM AUTHOR]

Modelling functionalities of the brain in human-robot interaction contexts requires a real-time understanding of how each part of a robot (motors, sensors, emotions, etc.) works and how they interact all together to accomplish complex behavioural tasks while interacting with the environment. Human brains are very efficient as they process the information using event-based impulses also known as spikes, which make living creatures very efficient and able to outperform current mainstream robotic systems in almost every task that requires real-time interaction. In recent years, combined efforts by neuroscientists, biologists, computer scientists and engineers make it possible to design biologically realistic hardware and models that can endow the robots with the required human-like processing capability based on neuromorphic computing and Spiking Neural Network (SNN). However, while some attempts have been made, a comprehensive combination of neuromorphic computing and robotics is still missing. In this article, we present a systematic review of neuromorphic computing applications for socially interactive robotics. We first introduce the basic principles, models and architectures of neuromorphic computation. The remaining articles are classified according to the applications they focus on. Finally, we identify the potential research topics for fully integrated socially interactive neuromorphic robots.

We have designed a fully-integrated analog CMOS cognitive image sensor based on a two-layer artificial neural network and targeted to low-resolution image classification. We have used a single poly 180 nm CMOS process technology, which includes process modules for realizing the building blocks of the CMOS image sensor. Our design includes all the analog sub-circuits required to perform the cognitive sensing task, from image sensing to output classification decision. The weights of the network are stored in single-poly floating-gate memory cells, using a single transistor per analog weight. This enables the classifier to be intrinsically reconfigurable, and to be trained for various classification problems, based on low-resolution images. As a case study, the classifier capability is tested using a low-resolution version of the MNIST dataset of handwritten digits. The circuit exhibits a classification accuracy of 87.8%, that is comparable to an equivalent software implementation operating in the digital domain with floating point data precision, with an average energy consumption of 6 nJ per inference, a latency of 22.5 $\mu \text{s}$ and a throughput of up to 133.3 thousand inferences per second.

Spiking Neural Networks (SNN) and the field of Neuromorphic Engineering has brought about a paradigm shift in how to approach Machine Learning (ML) and Computer Vision (CV) problem. This paradigm shift comes from the adaption of event-based sensing and processing. An event-based vision sensor allows for sparse and asynchronous events to be produced that are dynamically related to the scene. Allowing not only the spatial information but a high-fidelity of temporal information to be captured. Meanwhile avoiding the extra overhead and redundancy of conventional high frame rate approaches. However, with this change in paradigm, many techniques from traditional CV and ML are not applicable to these event-based spatial-temporal visual streams. As such a limited number of recognition, detection and segmentation approaches exist. In this paper, we present a novel approach that can perform instance segmentation using just the weights of a Spike Time Dependent Plasticity trained Spiking Convolutional Neural Network that was trained for object recognition. This exploits the spatial and temporal aspects of the SpikeSEG network's internal feature representations adding this new discriminative capability. We highlight the new capability by successfully transforming a single class unsupervised network for face detection into a multi-person face recognition and instance segmentation network. [ABSTRACT FROM AUTHOR]

This article explores the recent developments in spin-based domain wall (DW) memories. The physics behind the DW motion, device materials, current challenges, and applications have been discussed in detail. DWs can propagate through a magnetic nanowire by the application of external magnetic fields or by spin-polarized electric currents. Great progress has been made in these devices since the introduction of electric current-induced DW motion. However, driving DWs necessitates large spin-current densities that are incompatible with low-power devices. Therefore, significant efforts have been made to achieve highly efficient and controlled DW motion by material engineering and different mechanisms such as spin-orbit-torque (SOT), Dzyaloshinskii-Moriya interaction (DMI), and voltage-controlled magnetic anisotropy. The controlled manipulation of DWs in magnetic materials has inspired numerous strategies for high-density memory and energy-efficient logic implementation. Moreover, these devices are the potential candidates for neuromorphic computing applications that can be combined with logic-in-memory. The displacement of the DW can achieve multiple resistance states that have opened up possibilities of building artificial neurons and synapses. Despite the rapid progress, DW devices face several challenges such as low read margin, low speed, and sub-20nm scalability. Future research directions have to focus on material engineering and fabrication techniques to address these issues. Simultaneously, efforts from the circuit and system perspectives are extensively required in exploring the possible uses of these devices. [ABSTRACT FROM AUTHOR]

Traditional Von-Neumann computers would not meet the needs of storage and processing a large amount of information in the era of artificial intelligence owing to the separated storage and processing unit. Inspired by the human brain, various electronic devices have been developed for neuromorphic computing to conquer the von Neumann bottleneck. Organic synaptic transistors have attracted increasing interest due to their advantages of low cost, flexibility and ease of solution fabrication. However, most synaptic transistors based on the charge trapping principle use a single material, which limits the adjustment of synaptic plasticity. Here, a novel synaptic device based on a hybrid trapping layer was proposed and investigated. The device with a hybrid trapping layer exhibits a larger memory window than the device with a trapping layer based on single material, indicating that the device with hybrid trapping has a larger trapping capability. Moreover, our synaptic device was utilized to successfully simulate typical synaptic properties: excitatory postsynaptic current, inhibitory postsynaptic current, paired-pulse facilitation, paired-pulse depression and the transition from short-term plasticity to long-term plasticity. Furthermore, an artificial neural network was simulated and exhibited a high recognition accuracy. Therefore, the proposed device could promote the development of highly efficient neuromorphic computing systems. [ABSTRACT FROM AUTHOR]

Event cameras, offering extremely high temporal resolution and high dynamic range, have brought a new perspective to addressing common object detection challenges (e.g., motion blur and low light). However, how to learn a better spatio-temporal representation and exploit rich temporal cues from asynchronous events for object detection still remains an open issue. To address this problem, we propose a novel asynchronous spatio-temporal memory network (ASTMNet) that directly consumes asynchronous events instead of event images prior to processing, which can well detect objects in a continuous manner. Technically, ASTMNet learns an asynchronous attention embedding from the continuous event stream by adopting an adaptive temporal sampling strategy and a temporal attention convolutional module. Besides, a spatio-temporal memory module is designed to exploit rich temporal cues via a lightweight yet efficient inter-weaved recurrent-convolutional architecture. Empirically, it shows that our approach outperforms the state-of-the-art methods using the feed-forward frame-based detectors on three datasets by a large margin (i.e., 7.6% in the KITTI Simulated Dataset, 10.8% in the Gen1 Automotive Dataset, and 10.5% in the 1Mpx Detection Dataset). The results demonstrate that event cameras can perform robust object detection even in cases where conventional cameras fail, e.g., fast motion and challenging light conditions. [ABSTRACT FROM AUTHOR]

Organic materials with good biocompatibility and mechanical flexibility have great application potential in photonic neuromorphic computing. Here, the organic optoelectronic synapse for neuromorphic computing is fabricated on a flexible substrate. The excellent ferroelectricity of poly(vinylidene fluoride-trifluoroethylene) P(VDF-TrFE) endows the device with a memory window larger than 18 V and stable conductance modulation. The excellent photosensitive properties of 2,7-dioctyl[1] benzothieno[3,2-b][1]benzothiophene (C8-BTBT) enable the device to operate at an extremely low voltage of 0.25uV and achieve an ultralow energy consumption of 0.35fJ per event. In addition, under photoelectric dual modulation, the proposed synaptic devices can realize the simulation of biological synaptic behaviors, such as excitatory post-synaptic current (EPSC), long-term potentiation /depression (LTP/LTD). The neuromorphic computing function was verified using pattern recognition, with a recognition rate of up to 90.6% for handwritten digits. This research provides an effective way for the development of multifunctional artificial synaptic devices and artificial neural network systems. [ABSTRACT FROM AUTHOR]

In this article, a fully physically transient volatile memristor utilizing Mg as an active electrode with a structure of W/MgO/Mg/W was proposed. The fully transient device exhibited remarkable threshold switching (TS) performance via Mg2+ cations migration dynamics and emulated the paired-pulse facilitation (PPF), paired-pulse depression (PPD), and transition from short-term to long-term plasticity of a biological synapse successfully. In addition, a water-assisted transfer printing (WTP) method was exploited to fabricate the fully physically transient system on biodegradable and biocompatible substrates. This study confirms that the fully transient volatile memristor owns outstanding value toward security neuromorphic computing, biodegradable, and bio-integrated electronic systems. [ABSTRACT FROM AUTHOR]

CMOS devices display volatile characteristics and are not well suited for analog applications such as neuromorphic computing. Spintronic devices, on the other hand, exhibit both non-volatile and analog features, which are well suited to neuromorphic computing. Consequently, these novel devices are at the forefront of beyond-CMOS artificial intelligence applications. However, a large quantity of these artificial neuromorphic devices still require the use of CMOS to implement various neuromorphic functionalities, which decreases the efficiency of the system. To resolve this, we have previously proposed a number of artificial neurons and synapses that do not require CMOS for operation. Although these devices are a significant improvement over previous renditions, their ability to enable neural network learning and recognition is limited by their intrinsic activation functions. This work proposes modifications to these spintronic neurons that enable configuration of the activation functions through control of the shape of a magnetic domain wall track. Linear and sigmoidal activation functions are demonstrated in this work, which can be extended through a similar approach to enable a wide variety of activation functions. [ABSTRACT FROM AUTHOR]

Neuromorphic computing based on spiking neural networks (SNNs) has attracted significant research interest due to its low energy consumption and high similarity to biological neural systems. The artificial spiking afferent neuron (ASAN) system is the essential component of neuromorphic computing system to interact with the environment. This work presents an ASAN system with simple structure by employing a new architecture of one VO2 Mott memristor and one resistive sensor (1M1S). The Mott memristors show the bidirectional Mott transition, good endurance (> $1.3\times10$ 9), and high uniformity. By incorporating a flexible pressure sensor into the 1M1S architecture, a tactile ASAN system is realized with the pressure stimuli converted into rate-coded spikes. Using a $3\times3$ array of the tactile ASAN systems, different pressure stimulus patterns can be well recognized. The strong adaptability of the proposed system will enable it to convert lots of environmental stimuli through the widely used resistive sensors into rate-coded spikes as the inputs of neuromorphic computing based on SNNs. [ABSTRACT FROM AUTHOR]

The explosion of “big data” applications imposes severe challenges of speed and scalability on traditional computer systems. As the performance of traditional Von Neumann machines is greatly hindered by the increasing performance gap between CPU and memory (“known as the memory wall”), neuromorphic computing systems have gained considerable attention. The biology-plausible computing paradigm carries out computing by emulating the charging/discharging process of neuron and synapse potential. The unique spike domain information encoding enables asynchronous event driven computation and communication, and hence has the potential for very high energy efficiency. This survey reviews computing models and hardware platforms of existing neuromorphic computing systems. Neuron and synapse models are first introduced, followed by the discussion on how they will affect hardware design. Case studies of several representative hardware platforms, including their architecture and software ecosystems, are further presented. Lastly we present several future research directions. [ABSTRACT FROM AUTHOR]

This paper studies the suitability of neuromorphic event-based vision cameras for spaceflight and the effects of neutron radiation on their performance. Neuromorphic event-based vision cameras are novel sensors that implement asynchronous, clockless data acquisition, providing information about the change in illuminance $\ge 120dB$ with sub-millisecond temporal precision. These sensors have huge potential for space applications as they provide an extremely sparse representation of visual dynamics while removing redundant information, thereby conforming to low-resource requirements. An event-based sensor was irradiated under wide-spectrum neutrons at Los Alamos Neutron Science Center and its effects were classified. Radiation-induced damage of the sensor under wide-spectrum neutrons was tested, as was the radiative effect on the signal-to-noise ratio of the output at different angles of incidence from the beam source. We found that the sensor had very fast recovery during radiation, showing high correlation of noise event bursts with respect to source macro-pulses. No statistically significant differences were observed between the number of events induced at different angles of incidence but significant differences were found in the spatial structure of noise events at different angles. The results show that event-based cameras are capable of functioning in a space-like, radiative environment with a signal-to-noise ratio of 3.355. They also show that radiation-induced noise does not affect event-level computation. Finally, we introduce the Event-based Radiation-Induced Noise Simulation Environment (Event-RINSE), a simulation environment based on the noise-modelling we conducted and capable of injecting the effects of radiation-induced noise from the collected data to any stream of events in order to ensure that developed code can operate in a radiative environment. To the best of our knowledge, this is the first time such analysis of neutron-induced noise has been performed on a neuromorphic vision sensor, and this study shows the advantage of using such sensors for space applications.

A continuous attractor neural network (CANN) configured with various synaptic dynamics can implement many brain cognitive functions. Corresponding neuromorphic implementation can be beneficial to carry out these cognitive computations in real-time. Herein, we present a neuromorphic implementation of the CANN of spiking neurons on the field-programmable gate array (FPGA), in which the synaptic strength of local excitation and global inhibition can be configured to achieve winner-take-all (WTA) competition. In contrast to previously reported neuromorphic CANN, in addition to fast-linear synapses, recurrent connections can also be implemented with slow-nonlinear synapses. This endows the proposed CANN on the FPGA with the capability of performing neural computations that require slow and nonlinear temporal dynamics, such as decision making and working memory. Circuit simulations on the hardware reproduced gradually ramping neural activities observed in decision-making experiments and multiple sustained activities observed during the delay in working memory experiments, especially the fade-out and merging of activity bumps in the latter task. Theoretical analysis illuminated the underlying mechanisms of decision making and working memory on the FPGA. The unstable two-bump steady state of the CANN is responsible for the two-alternative decision making, similar to the saddle-node structure in the reduced two-variable decision model. Meanwhile, the stable uniformly distributed N-bump steady states account for the multiple-item working memory, similar to the multistability in previous mean-field models. Furthermore, the asymmetrical N-bump unstable steady states exhibit attractor dynamics underlying the fade-out and merging of activity bumps. The consistency between simulations on the hardware and the theoretical analysis demonstrated that the neuromorphic CANN is endowed with attractor dynamics relating to slow and nonlinear neural computations and has the potential to implement sophisticated cognitive functions by configuring various synaptic dynamics. This implementation shows promise for integrating the cognitive platform due to its characteristics of various dynamics and flexible configurations.

The aim of the article is to conceptualise a more compact and efficient version of algorithms for artificial intelligence (AI). The core objective is to construct the design for a self-optimising and self-adapting autonomous artificial intelligence (AutoAI) that can be applied for edge analytics using real-time data. The methodology is based on synthesising existing knowledge on AI (i.e., knowledge modelling, symbolic reasoning, modal logic), with novel concepts from neuromorphic engineering in combination with deep learning algorithms (i.e., reinforcement learning, neural networks, evolutionary algorithms) and data science (i.e., statistics, linear regression, Bayesian methods). Far-reaching implications are expected from the unique integration of approaches in neuromorphic engineering and edge analytics.

Brain-inspired approaches can efficiently analyze the activities of biological neural networks and solve computationally hard problems with energy efficiencies unattainable with von Neumann architectures, indicating a significant improvement in the understanding of neuronal communications and functionalities. Here, we present a brain-inspired multimodal signal processing system with organic memristor arrays that can potentially integrate the signal sensory, storage, and computation. To facilitate the multimodal signal processing system design, we used four components. First, we present a multimodal signal sensory module mainly responsible for multimodal (iconic, echoic, olfactory, muscular, and gustatory) signal collection, fusion, and storage. Second, a high-density cross-point memristive synapse array is constructed after fabrication of the albumin protein memristor to realize the dense connectivity between layers of computing, data storage, and communication. Third, considering the structure and function of the brain region, we demonstrate a general learning module for hierarchy learning, which can recognize and imagine multimodal information. Finally, the necessary peripheral circuit module (consisting of winnerless competition function circuit, analog-to-digital converter, digital-to-analog converter, pulse modulator, etc.) is designed. Notably, our system can capture massive amounts of data every second and perform in situ processing of multimodal signals. This study is expected to help achieve the deep integration of nano materials into neuromorphic computing systems and energy-efficient integrated circuits. [ABSTRACT FROM AUTHOR]

This paper presents a field-programmable gate array (FPGA) implementation of an auditory system, which is biologically inspired and has the advantages of robustness and anti-noise ability. We propose an FPGA implementation of an eleven-channel hierarchical spiking neuron network (SNN) model, which has a sparsely connected architecture with low power consumption. According to the mechanism of the auditory pathway in human brain, spiking trains generated by the cochlea are analyzed in the hierarchical SNN, and the specific word can be identified by a Bayesian classifier. Modified leaky integrate-and-fire (LIF) model is used to realize the hierarchical SNN, which achieves both high efficiency and low hardware consumption. The hierarchical SNN implemented on FPGA enables the auditory system to be operated at high speed and can be interfaced and applied with external machines and sensors. A set of speech from different speakers mixed with noise are used as input to test the performance our system, and the experimental results show that the system can classify words in a biologically plausible way with the presence of noise. The method of our system is flexible and the system can be modified into desirable scale. These confirm that the proposed biologically plausible auditory system provides a better method for on-chip speech recognition. Compare to the state-of-the-art, our auditory system achieves a higher speed with a maximum frequency of 65.03 MHz and a lower energy consumption of 276.83 μJ for a single operation. It can be applied in the field of brain-computer interface and intelligent robots. [ABSTRACT FROM AUTHOR]

Neuromorphic architectures have been introduced as platforms for energy-efficient spiking neural network execution. The massive parallelism offered by these architectures has also triggered interest from nonmachine learning application domains. In order to lift the barriers to entry for hardware designers and application developers, we present RANC: a reconfigurable architecture for neuromorphic computing, an opensource highly flexible ecosystem that enables rapid experimentation with neuromorphic architectures in both software via C++ simulation and hardware via FPGA emulation. We present the utility of the RANC ecosystem by showing its ability to recreate behavior of IBM’s TrueNorth and validate with a direct comparison to IBM’s Compass simulation environment and published literature. RANC allows optimizing architectures based on application insights as well as prototyping future neuromorphic architectures that can support new classes of applications entirely. We demonstrate the highly parameterized and configurable nature of RANC by studying the impact of architectural changes on improving application mapping efficiency with quantitative analysis based on Alveo U250 FPGA. We present post routing resource usage and throughput analysis across implementations of synthetic aperture radar classification and vector matrix multiplication applications, and demonstrate a neuromorphic architecture that scales to emulating 259K distinct neurons and 73.3M distinct synapses. [ABSTRACT FROM AUTHOR]

Continual learning is the ability to acquire a new task or knowledge without losing any previously collected information. Achieving continual learning in artificial intelligence (AI) is currently prevented by catastrophic forgetting, where training of a new task deletes all previously learned tasks. Here, we present a new concept of a neural network capable of combining supervised convolutional learning with bio-inspired unsupervised learning. Brain-inspired concepts such as spike-timing-dependent plasticity (STDP) and neural redundancy are shown to enable continual learning and prevent catastrophic forgetting without compromising standard accuracy achievable with state-of-the-art neural networks. Unsupervised learning by STDP is demonstrated by hardware experiments with a one-layer perceptron adopting phase-change memory (PCM) synapses. Finally, we demonstrate full testing classification of Modified National Institute of Standards and Technology (MNIST) database with an accuracy of 98% and continual learning of up to 30% non-trained classes with 83% average accuracy.

Many advances have been made in the field of computer vision. Several recent research trends have focused on mimicking human vision by using a stereo vision system. In multi-camera systems, a calibration process is usually implemented to improve the results accuracy. However, these systems generate a large amount of data to be processed; therefore, a powerful computer is required and, in many cases, this cannot be done in real time. Neuromorphic Engineering attempts to create bio-inspired systems that mimic the information processing that takes place in the human brain. This information is encoded using pulses (or spikes) and the generated systems are much simpler (in computational operations and resources), which allows them to perform similar tasks with much lower power consumption, thus these processes can be developed over specialized hardware with real-time processing. In this work, a bio-inspired stereo-vision system is presented, where a calibration mechanism for this system is implemented and evaluated using several tests. The result is a novel calibration technique for a neuromorphic stereo vision system, implemented over specialized hardware (FPGA - Field-Programmable Gate Array), which allows obtaining reduced latencies on hardware implementation for stand-alone systems, and working in real time.

Dynamic Vision Sensor (DVS) pixels produce an asynchronous variable-rate address-event output that represents brightness changes at the pixel. Since these sensors produce frame-free output, they are ideal for real-time dynamic vision applications with real-time latency and power system constraints. Event-based filtering algorithms have been proposed to post-process the asynchronous event output to reduce sensor noise, extract low level features, and track objects, among others. These postprocessing algorithms help to increase the performance and accuracy of further processing for tasks such as classification using spike-based learning (ie. ConvNets), stereo vision, and visually-servoed robots, etc. This paper presents an FPGA-based library of these postprocessing event-based algorithms with implementation details; specifically background activity (noise) filtering, pixel masking, object motion detection and object tracking. The latencies of these filters on the Field Programmable Gate Array (FPGA) platform are below 300ns with an average latency reduction of 188% (maximum of 570%) over the software versions running on a desktop PC CPU. This open-source event-based filter IP library for FPGA has been tested on two different platforms and scenarios using different synthesis and implementation tools for Lattice and Xilinx vendors.

Conductive bridge random access memory (CBRAM) has been concentrated recently for its ultrasmall size, low power consumption, synaptic characteristics, and application in neuromorphic computing. However, the accuracy of the CBRAM array-based neural network is not high enough due to the low linearity, limited ON/OFF ratio, and the number of states. The original illustration and the optimization methods are still paucity. In this work, the origin of the characteristics of CBRAM has been revealed from the filament distribution of the devices, which inspires us to design an inserted graphene structure of CBRAM and preset seeds leading to high linearity (0.995), ON/OFF ratio (26.4), and the number of states (63). The Monte Carlo simulation results reveal that the CBRAM with more seeds can promote a larger number of potential advantage path (PAP) conducing better characteristics. Moreover, the PAP can be modulated by the number of preset seeds. Finally, a handwritten recognition neural network has been realized by using a 1T-1R array, and high recognition accuracy (92%) has been obtained, which shows that devices with higher PAP can eventually promote higher recognition accuracy. [ABSTRACT FROM AUTHOR]

Neuromorphic hardware strives to emulate brain-like neural networks and thus holds the promise for scalable, low-power information processing on temporal data streams. Yet, to solve real-world problems, these networks need to be trained. However, training on neuromorphic substrates creates significant challenges due to the offline character and the required nonlocal computations of gradient-based learning algorithms. This article provides a mathematical framework for the design of practical online learning algorithms for neuromorphic substrates. Specifically, we show a direct connection between real-time recurrent learning (RTRL), an online algorithm for computing gradients in conventional recurrent neural networks (RNNs), and biologically plausible learning rules for training spiking neural networks (SNNs). Furthermore, we motivate a sparse approximation based on block-diagonal Jacobians, which reduces the algorithm’s computational complexity, diminishes the nonlocal information requirements, and empirically leads to good learning performance, thereby improving its applicability to neuromorphic substrates. In summary, our framework bridges the gap between synaptic plasticity and gradient-based approaches from deep learning and lays the foundations for powerful information processing on future neuromorphic hardware systems. [ABSTRACT FROM AUTHOR]

Accurate online classification of disturbance events in a transmission network is an important part of wide-area monitoring. Although many conventional machine learning techniques are very successful in classifying events, they rely on extracting information from PMU data at control centers and processing them through CPU/GPUs, which are highly inefficient in terms of energy consumption. To solve this challenge without compromising accuracy, this article presents a novel methodology based on event-driven neuromorphic computing architecture for classification of power system disturbances. A Spiking Neural Network (SNN)-based computing framework is proposed, which exploits sparsity in disturbances and promotes local event-driven operation for unsupervised learning and inference from incoming data. Spatio-temporal information of PMU signals is first extracted and encoded into spike trains and classification is achieved with SNN-based supervised and unsupervised learning framework. In addition, benefits of deep spiking networks for complex multi-class event identification problem are presented by leveraging increasing dynamic neural sparse spiking events with network depth. Moreover, a QR decomposition-based selection technique is proposed to identify signals participating in the low rank subspace of multiple disturbance events. Performance of the proposed method is validated on data collected from a 16-machine, 5-area New England-New York system. [ABSTRACT FROM AUTHOR]

Supervised, unsupervised, and reinforcement learning (RL) mechanisms are known as the most powerful learning paradigms empowering neuromorphic systems. These systems typically take advantage of unsupervised learning because they can learn the distribution of sensory information. However, to perform a task, not only is it important to have sensory information, but also it is required to have information about the context in which the system is operating. In this sense, reinforcement learning is very powerful for interacting with the environment while performing a context-dependent task. The predominant motivation for this brief is to present a digital architecture for a spiking neural network (SNN) model with RL capability suitable for learning a context-dependent task. The proposed architecture is composed of hardware-friendly leaky integrate-and-firing (LIF) neurons and spike timing dependent plasticity (STDP)-based synapses implemented on a field programmable gate array (FPGA). Hardware synthesis and physical implementations show that the resulting circuits can faithfully reproduce the outcome of a learning task previously performed in both animal experimentation and computational modelings. Compared to the state-of-the-art neuromorphic FPGA circuits with context-dependent learning capability, our circuit fires 10.7 times fewer spikes, which accelerates learning 15 times, while requiring 16 times less energy. This is a significant step in achieving fast and low-energy SNNs with context-dependent learning ability on FPGAs. [ABSTRACT FROM AUTHOR]

In this brief, we propose a novel energy-efficient temporal-spatial information processing circuit that serves as the signal pre-processing interface for spiking neural networks. In order to transform sensory information into a highly efficient neural-like spike train, an iteration encoding scheme based temporal-spatial inter-spike interval (ISI) encoder is designed and analyzed. Moreover, a decoder is designed with the spike-timing-dependent plasticity (STDP) principle, which performs well in information recovery. The prototype of the proposed ISI encoder is presented, with a 3-interval encoder through the standard 180nm CMOS technology. The proposed ISI encoder could operate in 1 MHz sampling frequency, and it occupies merely 0.647mm2 die area while consuming as low as 1.63 uW/neuron power. A multi-level ISI decoder with spike width adaptation is also designed and evaluated through the CIFAR10 image dataset. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) devices have been proposed to boost the density and the bio-realistic plasticity in neural networks. One of the main limitations to the development of neuromorphic systems with RRAM devices is the lack of compact models for the simulation of spiking neural networks, including neuron spike processing, synaptic plasticity, and stochastic learning. Here, we present a predictive model for neuromorphic networks with unsupervised spike timing-dependent plasticity (STDP) in HfO2 RRAM devices. Our compact model can predict the learning behavior of experimental networks and can speed up the simulation of unsupervised learning compared to Monte Carlo (MC) approaches. The model can be used to optimize the classification accuracy of data sets, such as MNIST, and to estimate the time of learning and the energy consumption. [ABSTRACT FROM AUTHOR]

Objective: Although biological synapses express a large variety of receptors in neuronal membranes, the current hardware implementation of neuromorphic synapses often rely on simple models ignoring the heterogeneity of synaptic transmission. Our objective is to emulate different types of synapses with distinct properties. Methods: Conductance-based chemical and electrical synapses were implemented between silicon neurons on a fully programmable and reconfigurable, biophysically realistic neuromorphic VLSI chip. Different synaptic properties were achieved by configuring on-chip digital parameters for the conductances, reversal potentials, and voltage dependence of the channel kinetics. The measured I-V characteristics of the artificial synapses were compared with biological data. Results: We reproduced the response properties of five different types of chemical synapses, including both excitatory ($AMPA$ , $NMDA$) and inhibitory ($GABA_A$ , $GABA_C$ , $glycine$) ionotropic receptors. In addition, electrical synapses were implemented in a small network of four silicon neurons. Conclusion: Our work extends the repertoire of synapse types between silicon neurons, providing greater flexibility for the design and implementation of biologically realistic neural networks on neuromorphic chips. Significance: A higher synaptic heterogeneity in neuromorphic chips is relevant for the hardware implementation of energy-efficient population codes as well as for dynamic clamp applications where neural models are implemented in neuromorphic VLSI hardware. [ABSTRACT FROM AUTHOR]

The paper develops a neuromorphic system on a Spartan 6 field programmable gate array (FPGA) board to generate locomotion patterns (gaits) for three different legged robots (biped, quadruped, and hexapod). The neuromorphic system consists of a reconfigurable FPGA-based architecture for a 3G artificial neural network (spiking neural network), which acts as a Central Pattern Generator (CPG). The locomotion patterns, are then generated by the CPG through a general neural architecture, which parameters are offline estimated by means of grammatical evolution and Victor-Purpura distance-based fitness function. The neuromorphic system is fully validated on real biped, quadruped, and hexapod robots.

Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of binary weights, which were demonstrated to have a limited accuracy reduction on many applications when quantization-aware training techniques are used. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse event-based data streams, while on-chip spike-based online learning appears as a key feature for applications constrained in power and resources during the training phase. However, designing power- and area-efficient SNNs still requires the development of specific techniques in order to leverage on-chip online learning on binary weights without compromising the synapse density. In this paper, we demonstrate MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86 mm $^2$ in 65-nm CMOS, achieving a high density of 738k synapses/mm $^2$. MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy tradeoff on the MNIST classification task compared to previously-proposed SNNs, while having no penalty in the energy-accuracy tradeoff. [ABSTRACT FROM AUTHOR]

An accurate description of muscular activity plays an important role in the clinical diagnosis and rehabilitation research. The electromyography (EMG) is the most used technique to make accurate descriptions of muscular activity. The EMG is associated with the electrical changes generated by the activity of the motor neurons. Typically, to decode the muscular activation during different movements, a large number of individual motor neurons are monitored simultaneously, producing large amounts of data to be transferred and processed by the computing devices. In this paper, we follow an alternative approach that can be deployed locally on the sensor side. We propose a neuromorphic implementation of a spiking neural network (SNN) to extract spatio-temporal information of EMG signals locally and classify hand gestures with very low power consumption. We present experimental results on the input data stream using a mixed-signal analog/digital neuromorphic processor. We performed a thorough investigation on the performance of the SNN implemented on the chip, by: first, calculating PCA on the activity of the silicon neurons at the input and the hidden layers to show how the network helps in separating the samples of different classes; second, performing classification of the data using state-of-the-art SVM and logistic regression methods and a hardware-friendly spike-based read-out. The traditional algorithm achieved a classification rate of $\text{84}\%$ and $\text{81}\%$ , respectively, and the spiking learning method achieved $\text{74}\%$. The power consumption of the SNN is $\text{0.05 mW}$ , showing the potential of this approach for ultra-low power processing. [ABSTRACT FROM AUTHOR]

Shifting computing architectures from von Neumann to event-based spiking neural networks (SNNs) uncovers new opportunities for low-power processing of sensory data in applications such as vision or sensorimotor control. Exploring roads toward cognitive SNNs requires the design of compact, low-power and versatile experimentation platforms with the key requirement of online learning in order to adapt and learn new features in uncontrolled environments. However, embedding online learning in SNNs is currently hindered by high incurred complexity and area overheads. In this paper, we present ODIN, a 0.086-mm $^2$ 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28-nm FDSOI CMOS achieving a minimum energy per synaptic operation (SOP) of 12.7 pJ. It leverages an efficient implementation of the spike-driven synaptic plasticity (SDSP) learning rule for high-density embedded online learning with only 0.68  $\mu$ m $^2$ per 4-bit synapse. Neurons can be independently configured as a standard leaky integrate-and-fire model or as a custom phenomenological model that emulates the 20 Izhikevich behaviors found in biological spiking neurons. Using a single presentation of 6k 16 × 16 MNIST training images to a single-layer fully-connected 10-neuron network with on-chip SDSP-based learning, ODIN achieves a classification accuracy of 84.5%, while consuming only 15 nJ/inference at 0.55 V using rank order coding. ODIN thus enables further developments toward cognitive neuromorphic devices for low-power, adaptive and low-cost processing. [ABSTRACT FROM AUTHOR]

Deep Learning algorithms have become state-of-the-art methods for multiple fields, including computer vision, speech recognition, natural language processing, and audio recognition, among others. In image vision, convolutional neural networks (CNN) stand out. This kind of network is expensive in terms of computational resources due to the large number of operations required to process a frame. In recent years, several frame-based chip solutions to deploy CNN for real time have been developed. Despite the good results in power and accuracy given by these solutions, the number of operations is still high, due the complexity of the current network models. However, it is possible to reduce the number of operations using different computer vision techniques other than frame-based, e.g., neuromorphic event-based techniques. There exist several neuromorphic vision sensors whose pixels detect changes in luminosity. Inspired in the leaky integrate-and-fire (LIF) neuron, we propose in this manuscript an event-based field-programmable gate array (FPGA) multiconvolution system. Its main novelty is the combination of a memory arbiter for efficient memory access to allow row-by-row kernel processing. This system is able to convolve 64 filters across multiple kernel sizes, from 1 × 1 to 7 × 7, with latencies of 1.3  $\mu$ s and 9.01  $\mu$ s, respectively, generating a continuous flow of output events. The proposed architecture will easily fit spike-based CNNs. [ABSTRACT FROM AUTHOR]

Spiking neural networks (SNNs) are being explored in an attempt to mimic brain's capability to learn and recognize at low power. Crossbar architecture with highly scalable resistive RAM or RRAM array serving as synaptic weights and neuronal drivers in the periphery is an attractive option for the SNN. Recognition (akin to “reading” the synaptic weight) requires small amplitude bias applied across the RRAM to minimize conductance change. Learning (akin to “writing” or updating the synaptic weight) requires large amplitude bias pulses to produce a conductance change. The contradictory bias amplitude requirement to perform reading and writing simultaneously and asynchronously, akin to biology, is a major challenge. Solutions suggested in the literature rely on time-division-multiplexing of read and write operations based on clocks, or approximations ignoring the reading when coincidental with writing. In this paper, we overcome this challenge and present a clock-less approach wherein reading and writing are performed in different frequency domains. This enables learning and recognition simultaneously on an SNN. We validate our scheme in SPICE circuit simulator by translating a two-layered feed-forward Iris classifying SNN to demonstrate software-equivalent performance. The system performance is not adversely affected by a voltage dependence of conductance in realistic RRAMs, despite departing from linearity. Overall, our approach enables direct implementation of biological SNN algorithms in hardware. [ABSTRACT FROM AUTHOR]

This brief presents the brainmorphic artificial intelligence (BMAI) project. The main goal is to generate a novel type of neuromorphic computing systems including novel algorithms and devices, which can achieve very high performance of artificial intelligence (AI) information processing with low power consumption and which can be very close to biological systems. To reach this goal, we developed biomimetic neural networks. Two systems have been designed, one analog chip and one digital system into FPGA. We present in this brief two applications of these biomimetic neural networks, one in AI with a pattern recognition algorithm and one in neuroscience for understanding the hearing system of Drosophila for designing a new asynchronous low-power sensor system in the future. [ABSTRACT FROM PUBLISHER]

Loihi is Intel’s novel, manycore neuromorphic processor and is the first of its kind to feature a microcode-programmable learning engine that enables on-chip training of spiking neural networks (SNNs). The authors present the Loihi toolchain, which consists of an intuitive Python-based API for specifying SNNs, a compiler and runtime for building and executing SNNs on Loihi, and several target platforms (Loihi silicon, FPGA, and functional simulator). To showcase the toolchain, the authors describe how to build, train, and use a SNN to classify handwritten digits from the MNIST database. [ABSTRACT FROM AUTHOR]