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Although metal/ferroelectric/semiconductor tunnel junctions have been attracting widespread interest as next-generation memory devices, only limited effort has been devoted so far to quantitatively address their current–voltage characteristics and their achievable memory window. In this article, we show experimental data on template Pt/BaTiO3/Nb:SrTiO3 tunnel junctions confirming, first of all, that large memory windows can be achieved in these devices when the switching of the electric polarization in the ferroelectric layer moves the substrate between an accumulation and a depletion condition. Besides, by measuring the current–voltage curve of the devices quickly after the set/reset pulses used for polarization switching, the importance of considering the detrimental effects of the large depolarization fields in the ferroelectric layer when assessing the device memory window is demonstrated. The experimental data are, then, reproduced by a model for electron transport through the junction accounting for both drift/diffusion and distributed tunneling in the semiconductor. The model allows to catch a comprehensive physical picture of device operation and represents a powerful tool for the design and optimization of ferroelectric tunnel junctions with semiconductor electrodes. [ABSTRACT FROM AUTHOR]

This paper investigates the temperature dependence of random telegraph noise (RTN) in 3-D NAND Flash technologies. Experimental results on memory arrays reveal an increase of RTN when temperature is reduced, which is mainly attributed to the growth of the amplitude of the fluctuations arising from RTN traps. A direct proof of this growth is provided by directly monitoring some RTN waveforms arising from single traps in cells out of either memory arrays or test elements. In order to explain this evidence, the TCAD model for polysilicon NAND strings presented in Part I of this paper is adopted and extended to address the amplitude of the threshold-voltage shift coming from the trapping of a single electron at different positions in cell channel. Numerical results successfully reproduce the experimental trends with temperature and allow to explain them in terms of stronger nonuniformities in polysilicon inversion when temperature decreases. In particular, the reduction of temperature makes the string currentmore controlledby the polysilicon grain boundaries, increasing, in turn, the amplitude of the RTN fluctuations arising from traps placed on or close to them. [ABSTRACT FROM AUTHOR]

This letter investigates the cycling dependence of random telegraph noise (RTN) in 3-D NAND Flash arrays. Experimental results reveal that cycling has a very weak impact on RTN in 3-D arrays, confirming even from this standpoint the general improvement in performance and reliability of these arrays with respect to their planar predecessors. In particular, even a large cycling dose of 10k program/erase cycles gives rise just to a slight increase of RTN, which is attributed to the growth of the average number of trap states contributing to the phenomenon. The statistical distribution of the amplitude of the single-trap RTN fluctuations is shown, instead, to be unaffected by cycling and to keep the same temperature sensitivity irrespective of the cycling dose. [ABSTRACT FROM AUTHOR]

This paper presents characterization and modeling results exploring the temperature dependence of the electrical characteristics of 3-D NAND Flash strings. Experimental data over a wide temperature range are used to calibrate a Technology Computer-Aided Design model for current transport through the polysilicon channel of the strings, which is then used to investigate the role of grain boundaries on string conduction. Results reveal that the variability in the grain configuration in the strings introduces a nonnegligible statistical spread in the temperature dependence of the threshold voltage (${V}_{T}$) of the memory cells, which acts as a broadening contribution to the array ${V}_{T}$ distribution when temperature is changed. The experimental and modeling activities will be extended in Part II of this paper to explore the temperature dependence of the ${V}_{T}$ instability caused by random telegraph noise. [ABSTRACT FROM AUTHOR]

This letter investigates the major differences between planar (2-D) and vertical-channel (3-D) NAND Flash memory arrays in terms of their temperature dependences. Attention is focused on three relevant parameters for memory array operation, namely, cell threshold-voltage, string saturation current, and width of the random telegraph noise distribution. Results highlight that the transition from2-D to 3-D arrays introduced non-negligible changes in the temperature behavior of these parameters, whose origin is traced back to the different channel material of the technologies, i.e., monocrystalline versus polycrystalline silicon. [ABSTRACT FROM AUTHOR]

By using our 16-nm NAND Flash technology as a test vehicle, in this paper, we summarize all the experimental evidence that we have gathered so far on the phenomenology of cycling-induced charge trapping/detrapping in Flash memories. In particular, results from experiments conceived to explore the dependence of charge detrapping on cell memory state reveal that the phenomenon involves more than the simple capture and emission of charge carriers in tunnel-oxide defects. Besides, the thermal activation of charge trapping is highlighted for the first time, along with the detailed dynamics leading to the increase of the trapped charge as cell cycling proceeds. These results allow to lay some cornerstones for the microscopic description of cyclinginduced charge trapping/detrapping in Flash memories. From these cornerstones, in the companion paper (Resnati et al., 2016), a new physical picture for the trapping/detrapping processes will be proposed and implemented in a statistical model able to reproduce their corresponding threshold-voltage instabilities over array lifetime. [ABSTRACT FROM PUBLISHER]

Starting from all the experimental evidence we presented in Part I of this work (Resnati et al., 2016), in this paper, we propose a new microscopic picture for cycling-induced charge trapping/detrapping in Flash memories. This picture involves structural relaxation of the charged tunnel-oxide defects as limiting step in the detrapping process, triggering the possibility for defects to exchange carriers with the substrate. This view is implemented in a statistical model able to reproduce the threshold-voltage instability coming from the phenomenon, including its dependence on cycling dose, temperature, and cell state during idle/bake periods. The model is then used to address some elaborated accelerated testing schemes commonly used to monitor charge trapping/detrapping and its related instability in Flash memories, explaining their results in the context of the new proposed picture of the phenomenon. [ABSTRACT FROM PUBLISHER]

This paper exploits the possibility of monitoring the floating-gate (FG) charge of state-of-the-art NAND Flash arrays with a single-electron resolution to investigate in detail the program operation and some previously inaccessible technological parameters. In particular, the analysis leads to the assessment of the statistical distribution of the FG to control-gate capacitance and of the leakage current from the FG through the intergate dielectric during the programming pulses. Results highlight that resolving the FG charge at the single-electron level opens new prospects for the investigation of the operation and the parameters of NAND Flash arrays. [ABSTRACT FROM AUTHOR]