10 results on '"Nouredine Rassoul"'
Search Results
2. Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications
- Author
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Hyungrock Oh, Attilio Belmonte, Manu Perumkunnil, Jerome Mitard, Nouredine Rassoul, Gabriele Luca Donadio, Romain Delhougne, Arnaud Furnemont, Gouri Sankar Kar, and Wim Dehaene
- Published
- 2021
3. Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM
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Lieve Teugels, Attilio Belmonte, H. Oh, Ludovic Goux, Ming Mao, Harinarayanan Puliyalil, Zsolt Tokei, Luka Kljucar, G. L. Donadio, Jerome Mitard, Diana Tsvetanova, Nouredine Rassoul, Harold Dekkers, K. Banerjee, Gouri Sankar Kar, Adrian Chasin, Romain Delhougne, M. J. van Setten, M. Pak, Subhali Subhechha, and Laurent Souriau
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010302 applied physics ,Reproducibility ,Materials science ,business.industry ,Transistor ,Dielectric ,01 natural sciences ,Power (physics) ,law.invention ,Capacitor ,law ,Logic gate ,0103 physical sciences ,Optoelectronics ,Wafer ,business ,Dram - Abstract
We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal V th reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (~3x10-19A/µm).
- Published
- 2020
4. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
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N. Jourdan, Katia Devriendt, E. Dupuy, Hans Mertens, S. Paolillo, Guillaume Boccardi, F. Schleicher, E. Sanchez, Romain Ritzenthaler, Frank Holsteyns, Z. Tao, Sylvain Baudot, Sofie Mertens, Haroen Debruyn, Kevin Vandersmissen, Thomas Chiarella, P. Morin, Antony Premkumar Peter, Anshul Gupta, Erik Rosseel, Min-Soo Kim, Nouredine Rassoul, Boon Teik Chan, Christopher J. Wilson, D. Radisic, Lieve Teugels, A. De Keersgieter, D. Yakimets, I. Demonie, N. Bontemps, C. Drijbooms, Sujith Subramanian, Bilal Chehab, Paola Favia, C. Lorant, Farid Sebaai, Steven Demuynck, Frederic Lazzarino, E. Dentoni Litta, G. Mannaert, Houman Zahedmanesh, Yong Kong Siew, J. Cousserier, T. Hopf, B. Briggs, Manoj Jaysankar, Jerome Mitard, K. Kenis, A. Sepúlveda, S. Wang, Naoto Horiguchi, Goutham Arutchelvan, E. Capogreco, O. Varela Pedreira, D. Zhou, Jürgen Bömmels, and Zsolt Tokei
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010302 applied physics ,Materials science ,business.industry ,chemistry.chemical_element ,02 engineering and technology ,Tungsten ,021001 nanoscience & nanotechnology ,01 natural sciences ,Electromigration ,Cmos scaling ,CMOS ,chemistry ,Booster (electric power) ,Logic gate ,0103 physical sciences ,Optoelectronics ,0210 nano-technology ,business ,Low resistance ,Scaling - Abstract
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.
- Published
- 2020
5. Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
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B. Parvais, G. Besnard, T. Zheng, Anne Vandooren, W. Li, Erik Rosseel, Julien Ryckaert, Nadine Collaert, Boon Teik Chan, Dan Mocuta, Nancy Heylen, E. Vecchio, Lan Peng, Juergen Boemmels, Liesbeth Witters, Steven Demuynck, Iuliana Radu, A. Khaled, G. Jamieson, Niamh Waldron, Philippe Matagne, Nouredine Rassoul, V. De Heyn, Amey Mahadev Walke, Gweltaz Gaudin, Walter Schwarzenbach, D. Radisic, Z. Wu, Katia Devriendt, Haroen Debruyn, Fumihiro Inoue, Bich-Yen Nguyen, Andriy Hikavyy, W. Vanherle, J. Franco, Lieve Teugels, Faculty of Economic and Social Sciences and Solvay Business School, Electronics and Informatics, Faculty of Engineering, Faculty of Medicine and Pharmacy, Human Physiology and Special Physiology of Physical Education, and Vriendenkring VUB
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010302 applied physics ,Materials science ,business.industry ,02 engineering and technology ,021001 nanoscience & nanotechnology ,01 natural sciences ,Line (electrical engineering) ,Threshold voltage ,Reduction (complexity) ,Reliability (semiconductor) ,Planar ,0103 physical sciences ,Thermal ,Electromagnetic shielding ,Optoelectronics ,Electrical and Electronic Engineering ,0210 nano-technology ,business ,NMOS logic - Abstract
3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the $I_{ON}$ performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.
- Published
- 2019
6. First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
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Liesbeth Witters, Z. Wu, Anne Vandooren, G. Mannaert, Nadine Collaert, E. Vecchio, Lars-Ake Ragnarsson, Romain Ritzenthaler, Niamh Waldron, V. De Heyn, Jerome Mitard, Nouredine Rassoul, Boon Teik Chan, Dan Mocuta, Bertrand Parvais, Veeresh Deshpande, Fumihiro Inoue, Lan Peng, Andriy Hikavyy, G. Jamieson, J. Franco, W. Vanherle, Lieve Teugels, T. Zheng, W. Li, Amey Mahadev Walke, Katia Devriendt, Erik Rosseel, Julien Ryckaert, Nancy Heylen, Steven Demuynck, Geert Hellings, Juergen Boemmels, Faculty of Economic and Social Sciences and Solvay Business School, Electronics and Informatics, Faculty of Engineering, Faculty of Medicine and Pharmacy, Human Physiology and Special Physiology of Physical Education, and Vriendenkring VUB
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010302 applied physics ,Materials science ,Silicon ,business.industry ,Stacking ,chemistry.chemical_element ,02 engineering and technology ,Dielectric ,Condensed Matter Physics ,021001 nanoscience & nanotechnology ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,Threshold voltage ,Dipole ,chemistry ,0103 physical sciences ,Materials Chemistry ,Optoelectronics ,Wafer ,Electrical and Electronic Engineering ,0210 nano-technology ,Tin ,business ,Immersion lithography - Abstract
3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(\mathrm{T}\leq 525^{\circ}\mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature.
- Published
- 2018
7. Key challenges and opportunities for 3D sequential integration
- Author
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E. Vecchio, T. Zheng, W. Li, Arindam Mallik, Liesbeth Witters, A. Hikkavyy, Nancy Heylen, Nadine Collaert, Fumihiro Inoue, Dan Mocuta, Z. Wu, Bertrand Parvais, Erik Rosseel, Julien Ryckaert, Niamh Waldron, J. Franco, Nouredine Rassoul, Lieve Teugels, Katia Devriendt, G. Jamieson, Juergen Boemmels, Anne Vandooren, G. Verbinnen, V. De Heyn, and Lan Peng
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010302 applied physics ,Computer science ,Transistor ,Stacking ,Silicon on insulator ,01 natural sciences ,Reliability engineering ,law.invention ,Low complexity ,CMOS ,law ,Logic gate ,0103 physical sciences ,Hardware_INTEGRATEDCIRCUITS ,Electronic circuit - Abstract
In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Junction-less devices are shown to be attractive top tier devices for low temperature processing, low complexity of fabrication and meeting reliability specification despite without the use of “reliability” anneal. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.
- Published
- 2018
8. Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling
- Author
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Nancy Heylen, G. Verbinnen, Amey Mahadev Walke, Anne Vandooren, T. Zheng, Erik Rosseel, W. Li, Fumihiro Inoue, E. Vecchio, V. De Heyn, Andriy Hikavyy, Z. Wu, Bertrand Parvais, Dan Mocuta, Lan Peng, Liesbeth Witters, J. Franco, Lieve Teugels, Arindam Mallik, Niamh Waldron, Nouredine Rassoul, G. Jamieson, Katia Devriendt, Veeresh Deshpande, Nadine Collaert, Faculty of Economic and Social Sciences and Solvay Business School, Electronics and Informatics, Work and Organisational Psychology, Faculty of Engineering, Faculty of Medicine and Pharmacy, and Human Physiology and Special Physiology of Physical Education
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Computer science ,Stacking ,wafer bonding ,Silicon on insulator ,02 engineering and technology ,law.invention ,law ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,Electrical and Electronic Engineering ,Safety, Risk, Reliability and Quality ,Scaling ,Electronic circuit ,business.industry ,020208 electrical & electronic engineering ,Transistor ,020206 networking & telecommunications ,silicon-on-insulator ,Semiconductor ,CMOS ,Hardware and Architecture ,Logic gate ,Systems engineering ,thermal budget ,junctionless ,business ,3D sequential - Abstract
In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.
- Published
- 2018
9. Subtractive Etch of Ruthenium for Sub-5nm Interconnect
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Victor Blanco, Gayle Murdoch, S. Paolillo, Danny Wan, Christoph Adelmann, Bogumila Kutrzeba Kotowska, Nouredine Rassoul, Frederic Lazzarino, Christopher J. Wilson, Jürgen Bömmels, Zsolt Tokei, and M. Ercken
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010302 applied physics ,Interconnection ,Materials science ,Annealing (metallurgy) ,business.industry ,Extreme ultraviolet lithography ,Copper interconnect ,chemistry.chemical_element ,02 engineering and technology ,021001 nanoscience & nanotechnology ,01 natural sciences ,Copper ,Ruthenium ,chemistry ,Electrical resistivity and conductivity ,0103 physical sciences ,Optoelectronics ,0210 nano-technology ,business ,Critical dimension - Abstract
Ruthenium has been recently considered as a promising candidate to replace copper as the BEOL interconnect material for sub-5nm technology nodes. In this work, single level Ru interconnects were fabricated in imec's 300-mm pilot line using EUV lithography and the subtractive etch of Ru films. Lines with critical dimension smaller than 10.5 nm were formed and electrically tested to assess the line resistance of patterned Ru. Using the TCR method, structures with resistivity of 15 μΩ.cm and cross-sectional area of 200 nm2 were obtained and benchmarked against analogous Ru and Cu damascene processes. Ru lines with aspect ratio up to 3.8 were fabricated and measured having line resistance below 500 Ω/μ $m$ at 12 nm CD. Ru is expected to outperform damascene Cu at this scale, supporting the potential insertion of Ru metal patterning for advanced technology nodes.
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- 2018
10. Extreme Thinned-Wafer Bonding Using Low Temperature Curable Polyimide for Advanced Wafer Level Integrations
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Erik Sleeckx, Serena Iacovo, Fumihiro Inoue, Lan Peng, Gerald Beyer, Alain Phommahaxay, Atsushi Nakamura, Kenneth Rebibs, Nouredine Rassoul, Eric Beyne, Julien Bertheau, and Andy Miller
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010302 applied physics ,Materials science ,Wafer bonding ,Polishing ,02 engineering and technology ,Substrate (printing) ,021001 nanoscience & nanotechnology ,01 natural sciences ,Grinding ,Chemical-mechanical planarization ,0103 physical sciences ,Wafer ,Adhesive ,Dry etching ,Composite material ,0210 nano-technology - Abstract
Extreme thinned wafer transfer technologies have been demonstrated by combining a selected set of temporary and permanent bonding materials. The extreme thinning was performed on the backside of a top wafer bonded on carrier wafer with the temporary glue material, subsequently followed by grinding, polishing and plasma dry etching to a final thickness of 5 µm. The properties of the temporary adhesive have been selected to be compatible with a permanent thermocompression bond of the extreme thin wafer to a final target substrate. Thus, the high thermal deformation resistance of the temporary adhesive is key. As we are dealing with extremely thin substrate, the required process uniformity and total thickness variation of each material are crucial. Hence after the spin-coating, the permanent bond polymer was planarized by a surface planer process. The performance benefit brought by this process and the final transfer steps will also be discussed.
- Published
- 2018
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