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The presence of multiple cores in modern multicore architectures makes thermal management and temperature estimation a really challenging task for enhancing reliability and lifespan. Due to the presence of many cores, the core/tile spacing needs to be optimized in order to enhance the thermal coupling between interconnect routing blocks and active tiles. In addition, the tiles activity patterns under partial workload conditions significantly affect the maximum on-chip temperature which results in nonuniform temperature distribution. This is due to poor thermal coupling between neighboring tiles owing to the decrease in spacing between cores. In this article, we investigate the thermal performance analysis of a 256-core (i.e., 64 tiles) Mempool reduced instruction set computer (RISC) V-based architecture considering the impact of inter tiles spacing. Simulation results reveal that lateral heat spreading predominantly affects the thermal performance in multicore architectures under partial workload conditions. We also optimize the thermal performance with different tiles activity pattern. Simulation results reveal that both the maximum on-chip temperature and lateral heat spreading are improved for specific tiles activity patterns. Also the thermal performance analysis considering the “tile-insite effect” reveals that there is little impact on on-chip maximum temperature ($T_{\text {max}}$), but the on-chip thermal gradient ($\Delta T$) and the thermal profile pattern are predominantly affected. Finally, the effect of the secondary heat path toward printed circuit board (PCB) is studied in this work. [ABSTRACT FROM AUTHOR]

Ring-based, resonant Si photonic (SiPho) devices are temperature sensitive and require thermal tuning for stable operation, which is accomplished with integrated metallic heaters. This paper investigates the combined electromigration (EM) and thermal performance of tungsten (W) heaters using calibrated electro-thermal finite element models. The current injectors that are used to supply the current to the heater are a known weak spot for electromigration. The presented modelling study shows the conflicting design requirements for optimal thermal performance and optimal EM performance, which results in the need of a careful trade-off, supported by experimental reliability data. Based on modelling results, new device designs are proposed with significant performance increase. Lastly, a new methodology is introduced which allows to predict the lifetime of the W-heaters, given specific operating conditions such as ambient temperature and required phase shift. [ABSTRACT FROM AUTHOR]

Thermal modeling of photonic integrated circuits (PICs) is required for circuit design and the development of thermal control algorithms. In this work, we present a methodology for obtaining a compact dynamic thermal $RC$ model of a PIC. PICs are sensitive to thermal coupling, and in this article, it is shown that traditional resistive coupling does not suffice, and a new coupling method is derived. The case study to which the new methodology is applied is a dense wavelength-division multiplexing ring filter with eight channels. With the obtained $RC$ model, the computational time is reduced from 5.5 h for finite element simulation to < 1 s for a single-step response. Using the compact model, circuit-level analysis of frequency response is carried out. Because of its high computational efficiency, the compact model opens possibilities for simulating thermal tuning algorithms. [ABSTRACT FROM AUTHOR]

Ring modulators for silicon photonic (SiPho) optical transceivers are extremely thermally sensitive and require thermal tuning for stable operation. This tuning is achieved with integrated heaters and in this work two aspects of the heaters are investigated: firstly, how to thermally model the heater-waveguide system in a SiPho ring modulator. Secondly, how to improve the energy efficiency by adapting the design in order to minimize the thermal tuning power consumed by the heater. Silicon substrate undercut (UCUT) is done in order to achieve out-of-plane thermal isolation and prevent heat flow directly into the Si substrate below the device. Introducing the UCUT increases the heater efficiency ($\eta _{h}$) with a factor X3.08. It is shown that the influence of the UCUT cross section on the heater efficiency can be neglected, only the total area and metals significantly influence the thermal behaviour. Comparison between electro-thermal and pure thermal simulation shows very similar behaviour. Finally, the UCUT causes an increase in thermal time constant with factor X3.68. [ABSTRACT FROM AUTHOR]

In this article, we design, demonstrate, and characterize a 3-D printed package-level polymer jet impingement cooling solution on a $23\times23$ mm2 thermal test chip. The experimental hardware results for a nozzle pitch of 2 mm show that, with 1-kW power dissipation, at a coolant (deionized (DI) water) flow rate of 3 liters per minute (LPM), the measured average chip temperature increase is ~65 °C with a cooler pressure drop of 0.15 bar between the inlet and outlet connections. It is also shown that bare die cooling without lid [and thermal interface material (TIM)] shows better cooling performance than the lidded package. Second, an advanced 3-D printed manifold with an additional flow redistribution structure is demonstrated. The experimental results show that the improved design achieves a better chip temperature uniformity compared to the reference design, showing a reduction of the chip temperature gradient with a factor of 4 and 2.3 for a flow rate of 0.5 and 3 LPM, respectively, while no significant impact on the cooler pressure drop was measured. The numerical modeling studies predict an additional 15.4% thermal performance improvement, by reducing the nozzle pitch from 2 to 1 mm, for a flow rate of 3 LPM. [ABSTRACT FROM AUTHOR]

This article presents the design, fabrication, experimental characterization, and modeling analysis of the chip-level hotspot targeted liquid impingement jet cooling for high-power electronics. The hotspot targeted jet impingement cooling concept is successfully demonstrated with a chip-level jet impingement cooler with a 1-mm nozzle pitch and 300- $\mu \text{m}$ nozzle diameter fabricated using high-resolution stereolithography (additive manufacturing). The computational fluid dynamics (CFD) modeling and experimental analysis show that the improved hotspot targeted cooler design with fully open outlets can reduce the on-chip temperature difference by 70% compared with the full array cooler at the same pumping power of 0.03 W. The local heat transfer coefficient can achieve 15 × 104 W/m2 K with a local flow rate per nozzle of 40 mL/min, requiring a pump power of 0.6 W. The benchmarking study proves that the hotspot targeted cooling is much more energy-efficient than uniform array cooling, with lower temperature difference and lower pump power. [ABSTRACT FROM AUTHOR]

The electromigration (EM) activation energy (EA) of alternative metals, such as Ru and Co, was obtained using low-frequency noise (LFN) measurements. High activation energies were expected, but values of ≈1 eV are found, most likely related to diffusion along with the metal-dielectric interface. Wafer-level accelerated EM tests were carried out to compare the LFN EA to the EM EA in the Ru wires. The calculation of the EM EA is found to be strongly dependent on the assumed temperature profile in the wire due to Joule heating (JH). The temperature profile was calculated analytically, assuming the contacts are at ambient temperature. For a void forming in direct proximity of the contact, the EM EA then matches the LFN EA. For a void at average wire temperature (ambient + JH), EA ≈ 2 eV. In addition to demonstrating the application of LFN to study EM in alternative metals, this article also cautions for the impact of JH on the calculation of EA in interconnects. [ABSTRACT FROM AUTHOR]

The chip-level bare die direct liquid impingement jet cooling is regarded as a highly efficient cooling solution for high-performance applications. Furthermore, it shows potential to be integrated inside the chip package. In previous studies, we demonstrated this cooling concept using a prototype fabricated with mechanical micromachining using polymers. With the improvement of fabrication resolution, additive manufacturing or 3-D printing technology enables the fabrication of low-cost polymer microjet coolers with complex internal 3-D geometries and allows easy customization of the cooler design. In this paper, a chip-level impingement jet cooler with a $4 \times 4$ jet array and 575- $\mu \text{m}$ nozzle diameter is fabricated with high-resolution stereolithography, and assembled directly on the top of the bare die. The modeling study shows that the pressure drop in the 3-D printed cooler is reduced by 24% compared to the micromachined (MM) cooler with the same nozzle dimensions thanks to an improved more complex internal geometry. The fabrication quality and tolerances of the printed cooler are evaluated using optical measurements, scanning acoustic microscope (SAM) inspection, and cross-sectional analysis, showing a measured average nozzle diameter of 575 $\mu \text{m}$ compared to the designed nozzle diameter of 600 $\mu \text{m}$. Moreover, the 3-D computational fluid dynamics (CFD) simulations used in this paper are experimentally validated by chip temperature measurements. The achieved minimal thermal resistance of 3-D printed $4 \times 4$ cooler is 0.16 cm $^{2}\cdot \text{K}$ /W for a flow rate of 1000 mL/min. The benchmarking study shows the cooler size can be reduced by a factor of 6.5 by using the 3-D printing technology compared to the MM cooler. [ABSTRACT FROM AUTHOR]

A high-efficiency three-dimensionally (3-D) shaped polymer multi-jet impingement cooler based on cost-efficient fabrication techniques is introduced for the cooling of high-power applications. State-of-the-art highly efficient multi-jet cooling solutions rely on expensive Si or ceramic fabrication techniques, while low-cost cooling solutions have been proposed for less performant single-jet impingement. In this paper, we present the concept, modeling, design, fabrication, experimental characterization, and benchmarking with literature data of a multi-jet impingement based liquid cooling solution, fabricated using low-cost polymer fabrication techniques, targeted to directly cool the backside of high-power devices. For the modeling study, unit cell model and full system level models are used to study the nozzle array scaling trends and thermal and fluidic jet-to-jet interactions. Furthermore, design guidelines for high-power electronics cooling are provided, including geometry selections, material selection, and fabrication techniques. Based on the design guidelines and cooling concept, this paper demonstrates a 3-D-shaped polymer impingement cooler with a 4 × 4 nozzle array, showing a very good thermal performance with low required pumping power. The multi-jet cooler can achieve heat transfer coefficients up to 6.25 × 104 W/m2·K with a pump power as low as 0.3 W. The benchmarking study confirms furthermore that multi-jet cooling is more efficient than single-jet cooling and that direct cooling on the backside of the semiconductor device is more efficient than cooling the substrate or base plate. [ABSTRACT FROM AUTHOR]

In this paper, the transient experimental validation of the convolution-based fast thermal model (FTM) for 3-D integrated circuits is presented. The methodology is proven to be applicable to analyze the temperature evolution of real devices. A low-power package configuration with two different power dissipation scenarios, hotspot (HS) in the corner and HS in the center of the active region, has been considered for the validation. In this way, the importance of the package thermal impact on the definition of the final temperature profiles is highlighted. The error between the measurement and the FTM results remains always below 2.3 °C/W. Moreover, the model has been validated with respect to case studies concerning duty cycles of different durations. This proves the applicability of the model in defining the allowed duration of the chip activity before a maximum threshold temperature is reached. Finally, in this paper, the possibility to use a variable time-step approach in the transient FTM is presented together with the option of computing the temperature in individual points only. This is possible maintaining the same accuracy as if the fully resolved temperature maps would be calculated. [ABSTRACT FROM AUTHOR]

In this paper, several experimental methods (electrical and optical) for channel temperature detection in AlGaN/GaN high-electron mobility transistors have been studied and experimentally benchmarked. This paper encompasses four electrical methods (two dc characterization methods, low-RF output conductance measurement, and gate-resistive sensing technique) and one optical method (micro-Raman spectroscopy), which have been frequently used to sense temperature in AlGaN/GaN transistors. The experiments are carried out on identical test structures on wafer-level conditions as well as on single dies mounted on printed circuit board for power densities up to 12 W/mm. Due to a large temperature distribution along the channel of the devices and due to the physics on which each method is based, it was shown that the differences between the measured temperatures using the different methods can be as high as 50%. Experimental results are discussed and compared with coupled TCAD and finite element modeling simulations, where significant agreements have been observed. [ABSTRACT FROM AUTHOR]

The relevance of accurate prediction of the thermal behavior of microelectronic systems has been increasing since the introduction of 3D integrated circuits (ICs). Different modeling strategies have been implemented to this scope, aiming both to increase accuracy and to reduce computational time. In this paper, a transient fast thermal model methodology for packaged 3D stacked ICs is presented. It can be considered as a multiscale strategy, whose core is constituted by a highly resolved, convolution-based algorithm. This allows to compute the temperature increase due to a generic, time varying, power map in a stack configuration. On top of this, the time-dependent package thermal spreading and capacitive effect is included via correction profiles. These corrections are based on the ratio between the thermal responses of the package and of the stack configurations to uniform, impulsive, power dissipation at different time steps. Validation with respect to finite-element method results shows good accuracy. An error metric, to estimate a priori the need to include the package impact on top of the convolution-based approach, has also been developed. Alternative but similar algorithms, which place themselves in between the solutions with and without the package impact, both from an accuracy and from a computational time point of view, are also shortly presented in this paper. [ABSTRACT FROM AUTHOR]

Thermal analysis of AlGaN/GaN high-electron mobility transistors on silicon has been performed with emphasis on the influence of the field-plate configuration on power dissipation and temperature profiles along a 2-D electron gas. The results highlight the importance of the field plates in power dissipation and show the difference between various field-plate configurations. Consequently, their design is important for a good thermal behavior and reliability of the transistors. By means of coupled technology computer aided design and finite element modeling simulations, a model is developed and used to characterize test structures in the saturation regime for power densities up to 12 W/mm. In addition, experiments are presented providing RF extraction of the ac output conductance and showing the influence of self-heating in a wide frequency range. In this way, the thermal resistance is extracted. The measured results are in good agreement with the electrothermal model. [ABSTRACT FROM AUTHOR]

In this paper, we present test structures and measurement techniques that enable the extraction of the significance of the thermal–mechanical stress in 3D-stacked integrated circuit technology. Heaters and integrated diodes have been used to determine the impact of hotspots in 3-D systems. The results obtained showed that in 3-D case, the peak temperature of a hotspot is three times higher compared to a traditional 2-D system. For the characterization of through silicon vias (TSVs)-induced stress and its impact on analog metal-oxide semiconductor (MOS) devices, a 10-bit current steering digital-to-analog converter (DAC) test structure is utilized. The DAC has been optimized to detect ion changes down to 0.5% due to TSV proximity, TSV orientation, thermal hotspots, and wafer thinning or stacking process. The results obtained from stand-alone short-channel MOS devices and the DAC structure clearly indicate the impact of TSV proximity and TSV orientation on the carrier mobility of nearby transistors. [ABSTRACT FROM PUBLISHER]

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes Vth shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 \ mm^2) and power (3%) overhead. [ABSTRACT FROM AUTHOR]

In this paper, the capability of a novel cooling system for microchannels based on the principle of electrowetting is examined. To start with, the electrowetting effect in microchannels is experimentally investigated. The used electrowetting system consists of a liquid droplet deposited on a conductive Si substrate and electrically insulated from this substrate by a dielectric layer. Microchannels of 100 μm × 100 μm are etched in the substrate. By applying an ac voltage signal between the droplet and the substrate, the microchannels can be periodically filled and emptied with the liquid of the droplet. This oscillating liquid flow will be used to cool the chip. For the 100 μm × 100 μm microchannels a voltage of 51 V is required for the actuation. Further, based upon the results of the filling of the channels the cooling capacity of the proposed system is theoretically investigated. The theoretically achievable cooling rate of this enhanced system is compared to the heat transfer by conduction through a silicon substrate. A critical filling period is found; for shorter filling periods, the heat transfer will be improved by inserting microchannels, for higher filling periods the electrowetting deteriorates the cooling. It can be concluded that the proposed system is promising, especially when frequencies in the range of a few Hz can be achieved. [ABSTRACT FROM AUTHOR]

AlGaN/GaN high electron mobility transistors (HEMT) on sapphire substrates have been studied for their potential application in RF power applications; however, the low thermal conductivity of the sapphire substrate is a major drawback. Aiming at RF system-in-a-package, the authors propose a flip-chip-integration approach, where the generated heat is dissipated to an AlN carrier substrate. Different flip-chip-bump designs are compared, using thermal simulations, electrical measurements, micro-Raman spectroscopy, and infrared thermography. The authors show that a novel bump design, where bumps are placed directly onto both source and drain ohmic contacts, improves the thermal performance of the HEMT. [ABSTRACT FROM AUTHOR]