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Your search keyword '"Oster, Matthias"' showing total 4 results
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4 results on '"Oster, Matthias"'

3. CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory--Processing--Learning--Actuating System for High-Speed Visual Object Recognition and Tracking.

Author

Gotarredona, Rafael Serrano, Oster, Matthias, Lichtsteiner, Patrick, Linares-Barranco, Alejandro, Paz-Vicente, Rafael, Gómez-Rodríguez, Francisco, Camuñas-Mesa, Luis, Berner, Raphael, Rivas-Pérez, Manuel, Delbrück, Tobi, Liu, Shih-Chii, Douglas, Rodney, Häfliger, Philipp, Jiménez-Moreno, Gabriel, Ballcels, Anton Civit, Serrano-Gotarredona, Teresa, Acosta-Jiménez, Antonio J., and Linares-Barranco, Bernabé

Subjects
*CENTRAL nervous system, *NEURONS, *NEURAL transmission, *PHYSIOLOGY, *COMMUNICATION
Abstract

This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing- learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asychronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. has four custom mixed-signal AER chips, five custom digital AER interface components, 45k neurons (spiking cells), up to 5M synapses, performs 12G synaptic operations per second, and achieves millisecond object recognition and tracking latencies. [ABSTRACT FROM AUTHOR]

Published
2009
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4. Quantification of a Spike-Based Winner-Take-All VLSI Network.

Author

Oster, Matthias, Wang, Yingxue, Douglas, Rodney, and Liu, Shih-Chii

Subjects
*INTEGRATED circuits, *NONLINEAR functional analysis, *DIGITAL electronics, *ARTIFICIAL neural networks, *COMPUTATIONAL mathematics, *NEURAL computers, *COMPUTER networks, *COMPUTER systems
Abstract

We describe a formalism for quantifying the performance of spike-based winner-take-all (WTA) VLSI chips. The WTA function nonlinearly amplifies the output responses of pixels/neurons dependent on the input magnitudes in a decision or selection task. In this paper, we show a theoretical description of this WTA computation which takes into consideration the input statistics, neuron response variance, and output rates. This analysis is tested on a spiking VLSI neuronal network fabricated in a 4-metal, 2-poly 0.35-μm CMOS process. The measured results of the WTA performance from this chip correspond to the theoretical prediction. This formalism can be applied to any implementation of spike-based neurons. [ABSTRACT FROM AUTHOR]

Published
2008
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