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This paper discusses quantum computing with a strong focus on quantum software, quantum networks, quantum simulation, and applications. The study on quantum speedups reveals fundamental differences between quantum algorithms and classical algorithms. As a case study, further improvement on Shor's algorithm is presented with experimental results. The study shows that quantum circuits can be generated automatically to further improve the efficiency of quantum algorithms.

The paradigm of quantum computation has led to the development of new algorithms as well variations on existing algorithms. In particular, novel cryptographic techniques based upon quantum computation are of great interest. Many classical encryption techniques naturally translate into the quantum paradigm because of their well-structured factorizations and the fact that they can be phased in the form of unitary operators. In this work, we demonstrate a quantum approach to data encryption and decryption based upon the McEliece cryptosystem using Reed-Muller codes. This example is of particular interest given that post-quantum analyses have highlighted this system as being robust against quantum attacks. Finally, in anticipation of quantum computation operating over binary fields, we discuss alternative operator factorizations for the proposed cryptosystem.

In this paper, we present a multi-factor stateful authentication system that uses Near Field Communication (NFC) technology, a mobile phone, known pictures, and state (time sequence) to authenticate users. A user firstly accesses to the mobile phone and then emulates encrypted NFC tags through a mobile app. This mobile app forwards an authentication code to the computer after correctly selecting a preset picture. A custom process bypasses the built-in OS access control letting the user to type a passcode to gain access to the computer. The custom access control process running on the computer is programmed by using an open source credential provider and a database that stores the encrypted authentication codes. Our experiments show that this multi-factor and stateful authentication prevents man-in-the-middle attacks and improves security with a simplified login process.

Excessive CO 2 emission in the atmosphere has been proved to cause extreme weather events such as heavy rain, violent storm, droughts and heat waves. Recent study from Max Plank Institute for Biogeochemistry, Germany1 indicates the extreme events not only cause suffers in the whole ecosystems but also create more CO 2 emission to form a climate change vicious circle due to self-reinforcing effect. Reducing CO 2 emission is the most urgent endeavor in environmental protection to ensure the sustainability of tour planet ecosystems. Reducing CO 2 emission through alternative material application such as lower soldering temperature can be a potential major contribution from electronic industry. iNEMI Board Assembly Technical Roadmap2 of 2017 predict that the low temperature soldering (LTS) usage will increase to 20 plus percent by 2027. The drivers for this LTS technology trend are three folds, the energy and CO 2 emission reduction, overcome material limitation in electronic component and PCB, and low soldering process to match with electronic miniaturization.This article is part 1 of a series of study on new low melting temperature solder interconnect application and reliability on various product categories, enterprise computers such as server and storage, AIO (all-in-one desk top), POS (Point of Sale), tablet, and automotive electronics. First, the raw LTS SnBiAg material properties range from power particle size, Halogen content, flux characterization, viscosity, wetting, SIR, Electrochemical migration etc. are assessed. Then five product emulators are selected as test vehicle to represent the broad scope of various electronics products. Due to the nature of brittleness of Bi contain in the LTS as shown in earlier publications2,3 the material drop cycle to failure reliability of LTS is substantially below current SAC305 which widely used in various electronics. Mechanical strengthening mechanism such as corner bonding material is attached along the BGA to observe the susceptibility of mechanical shock in later two product emulators, tablet and automotive electronics.Since all BGA incoming with solder composition are in SAC305 nowadays there is a backward compatibility issue with new LTS. Inhomogeneous microstructure as well as potential solder defect was observed in SEM micrograph. Experiment of adding various LTS paste volume so as different Bi percentage in mixed alloy join are studied to see crack propagation and failure interface due to Bi diffusion and intermetallic compound formation when product emulator subject to accelerated stress test. While observe the crack propagation in microstructure, potential strengthening mechanism such as solid solution, precipitation hardening and phase size refinement can be determined in the of SAC and LTS mixed and Bi percentage variation alloy.Finally BFT (board functional test) will be conducted in between accelerated thermal and mechanical cycling test to offline but real-time monitoring the reliability of solder joint of passive, PTH, BGA of active IC and CPU. The benefit of using product emulators with BFT is an advantage in the transition of LTS from SAC.

This article is a series of study on new generation of electronic contact challenges and component interconnects technology for high-end computing products. These products include server and data storage for cloud computing applications at the data center as well as core routers for service providers, edge and branch routers for enterprise networking companies, and small switch and wireless router for commercial and small and home office. All these cloud computing products require high data speed in terabytes per second and high signal integrity for the massive mobile users and IoT application whenever and wherever they connected.

This article is Part 2 of a series of studies on new generation of electronic challenges and interconnect process technologies for networking computer products. These products include core routers for service providers, edge and branch routers for enterprise networking companies, small switch and wireless router for commercial and SOHO (small and home office), as well as server and data storage for cloud computing applications at the data center. All these cloud computing products require high data speed in terabytes per second and high reliability for the new generation of mobile users, whenever and wherever they are. Super mobility and high reliability are the backbone for this big dream of internet anywhere.

This article is part 1 of a series of study on new generation of electronic challenging and interconnects process technology for networking computer products such as core router for service provider, edge and branch router for enterprise networking companies, and small switch and wireless router for commercial and SOHO (small and home office). All these networking products require high data speed in tera bits per second and high reliability for new generation of mobile user whenever and wherever they are. The super mobility and reliability performances are backbone for this big dream of networking.

Smart city opens up data with a wealth of information that brings innovation and connects government, industry and citizens. Cyber insecurity, on the other hand has raised concerns among data privacy and threats to smart city systems. In this paper, we look into security issues in smart city infrastructure from both technical and business operation perspectives and propose an approach to analyze threats and to improve data security of smart city systems. The assessment process takes hundreds of features into account. Data collected during the assessment stage are then imported into an algorithm that calculates the threat factor. Mitigation strategies are provided to help reducing risks of smart city systems from being hacked into and to protect data from being misused, stolen or identifiable. Study shows that the threat factor can be reduced significantly by following this approach. Experiments show that this comprehensive approach can reduce the risks of cyber intrusions to smart city systems. It can also deal with privacy concerns in this big data arena.

This paper summarizes development of the ISGAN (International Smart Grid Action Network) framework of assessment culminating with identification of the first biennial assessment results of smart grid motivating driver and technology priorities at both the national level and multinational level. As of 5 September 2012, 19 ISGAN Participants had completed and validated 27 assessments via the developed web-based assessment tool. A methodology devised with weighting schemes for motivating drivers and smart grid technologies has allowed clustering analyses of these assessments at the national level and multinational level. Clustering analyses for all ISGAN Participants, as well as of Participants by economies and by continent, were conducted; these multinational-level prioritized assessment results are provided herein. The national-level prioritized assessment results have been used to identify smart grid projects for data collection for the ISGAN Inventory that is intended to serve as a global resource on smart grid activities across ISGAN Participants.

The evolution in semiconductor and electronic packaging to fulfill mobility and miniaturization has drastically changed the nature of electronic industry. Electronic component are continuing to get more sensitive to EOS (electrical overstress) due to electrostatic Sensitivity, Although HBM (Human Body Model) for Electrostatic sensitive device (ESD) has not changed for the last two decades. In this article, the CDM (Charged Device Model) which is used in semiconductor device ESD sensitivity test will be explained for a potential situation where a semiconductor device is charged to a high voltage then discharged to a grounded surface. From the failure analysis data collected from the field in the past several years, it is clear that the number of failure caused by ESD has been increasing due to component electrostatic as sensitivity as 100V of CDM. It is perilous to find out the possible ESD source and risk in PCBA/SYS assembly process and make the corresponding remedy before the electronic board is build in the line. This article will give the general guideline to make this extended ESD control, and a working model will be developed to organize the mitigation plan and measures to be taken.

Video data is a major format of unstructured data, and should be an indispensable area of big data analytics. Existing search engines and data analytics tools such as Google, SAS, SPSS and Hadoop are effective only in analyzing text and image data. Video data analytics are often neglected due to the complexity and challenges in penetrating into videos.

• For 2014, US defense and technology analysts are in agreement that big data and cybersecurity are the two drivers in planning and investment for information technology, both in government and in industry. • Navy is proposing emerging maritime strategy of command, control, communications, computers, intelligence, surveillance and reconnaissance (C4ISR) with big data.

Joining methods based on self-propagating reaction have been presented in the field of electronic packaging to solve the mismatch of CTEs (Coefficient of thermal expansion) among materials. As a key factor for joining reliability, the defects should be minimized to obtain the sound and reliable solder joints. However, due to the very fast heating and cooling speeds, the solder behavior and the formation mechanism of defects in self-propagating joining are different from that in traditional joining methods. In this study, the interfacial IMC morphology, defects in joints and the fracture behavior had been characterized to enable an analysis and evaluation of the solder behavior and formation of defects in self-propagating joints. In addition, the influence of material properties, applied pressure and ambient temperature had been investigated which can assist further optimization of process and the joining quality.

Reliability of compliant pin interconnects due to design parameter is critical to ensure product performance is maintained at pre-defined shipping condition and user environment. Plating thickness of compliant pin and damping mechanism of electronic system are key successful factor in this regard. In additional transportation and material handling process of a server system will be affected by shock under certain conditions. Many accessories in the server system tend to become loose resulting in poor contact problems due to the severity of shock in the transportation and material handling processes. In this article, design variables such as pin hard-Au plating thickness, Mother Board locking mechanism and damping plat are experimented and reviewed. Also shocklog device is used to monitor the acceleration, duration and direction of shock realtime in large stationary or moving systems in transportation and transferring process. The data collected can be used to calculate the shock energy level. The comparison between the value of shock energy level and the criterion can be used to judge whether the shock can cause poor contact problems in transportation and transferring process. These design variables and stresses can be evaluated by drop test or vibration test to ensure system functional integrity is achieved.

A multipurpose of the performance measuring system for the phase change heat transport device such as heat pipe, vapor chamber and defrost plate was designed in this study. The characteristic of this measuring system was using thermal electrical chip (T.E.C.) as the condenser. This paper also present experimental measurement of performance of a vapor chamber (VC), heat pipe and defrost plate. The vapor chamber, with square sides of 50 × 50mm and thickness of 3.5mm and 6mm, was sandwiched between a heater block and a cooling plate located on the evaporator and the condenser surface respectively. The performance of the vapor chamber was investigated by determining the thermal resistance over a heat input range of 1 to 5W in natural convection test with the condenser opens at ambient environment and up to 40W in force convection with the condenser held at constant temperature. The experimental results show that the Maximum heat dissipated ability was the same compare with the new design measuring system and the traditional heat pipe performance measuring system with a water jacket as the cooling condenser. The thermal resistance in natural convection condition for the axial direction was around 0.1°C/W, while the spray thermal resistance was 0.12°C/W. For the defrost plate, the axial thermal resistance was 0.17°C/W and 0.18°C/W for the spray thermal resistance.

PTH often suffers poor hole fillet in wave soldering on OSP PCB. When PCB thickness reaches 2.7mm in server products and when the process is of lead-free, this issue has become more and more prominent. This paper studies how to achieve a good hole fillet by a good design of PTH hole. Two main factors are discussed here — GND layer and Gap between the hole and the component pin. With minimum GND layers under electrical requirement and gap ratio of 15–20% (gap between PTH wall and PTH component pin is of (15–20%) ∗2.70mm, i.e. 0.40–0.54mm), a good hole fillet can be guaranteed. Further study also shows that such process parameters as flux volume and dipping time can be optimized to enhance wave solder capability and PCBA reliability when GND layer is reduced and hole diameter is enlarged. Further study also shows that flux type ought to be of high activity in dealing with 2.7-mm-thick PCB with surface finish of Enthone HT OSP type.

Oxidation on PCB due to shelf life and environment stresses is a severe problem in the soldering process. In this article, the chemical agent of Silver Nitric is used to react with OSP coated-cupper pad. By measuring the time to discoloration, the severity of oxidation can be quantitatively classified by solder wettibility. Variables such as storage time, temperature & humidity, reflow cycles are adapted as preconditioning to emulate shelf life and environment stress and to use as failure precipitation mechanism for oxidation on cupper pad. Using discoloration as an innovative process indicator, the hardening of OSP coating can also be reviewed.

This paper highlights the U.S. Department of Energy's Smart Grid R&D projects on dynamic optimization of distribution grid operations through integration of advanced sensing, communication, and control technologies. The progress and planned activities of the following programs are discussed: Renewable and Distributed Systems Integration demonstrations, microgrid developments, the Smart Grid Regional Demonstrations, and five new projects from the FY 2010 Smart Grid RD&D Funding Opportunity Announcement. In addition, potential focus areas for the Smart Grid R&D Program in FY 2011 are presented.