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Clock synchronization procedures are mandatory in most physical experiments where event fragments are readout by spatially dislocated sensors and must be glued together to reconstruct key parameters (e.g. energy, interaction vertex etc.) of the process under investigation. These distributed data readout topologies rely on an accurate time information available at the frontend, where raw data are acquired and tagged with a precise timestamp prior to data buffering and central data collecting. This makes the network complexity and latency, between frontend and backend electronics, negligible within upper bounds imposed by the frontend data buffer capability. The proposed research work describes an FPGA implementation of IEEE 1588 Precision Time Protocol (PTP) that exploits the CERN Timing, Trigger and Control (TTC) system as a multicast messaging physical and data link layer. The hardware implementation extends the clock synchronization to the nanoseconds range, overcoming the typical accuracy limitations inferred by computers Ethernet based Local Area Network (LAN). Establishing a reliable communication between master and timing receiver nodes is essential in a message-based synchronization system. In the backend electronics, the serial data streams synchronization with the global clock domain is guaranteed by an hardware-based finite state machine that scans the bit period using a variable delay chain and finds the optimal sampling point. The validity of the proposed timing system has been proved in point-to-point data links as well as in star topology configurations over standard CAT-5e cables. The results achieved together with weaknesses and possible improvements are hereby detailed., Comment: 8 pages, 14 figures, proceedings of 21st IEEE Real Time Conference Colonial Williamsburg 9-15 June 2018

Este artigo propoe a aplicacao do controle preditivo baseado em modelo (MPC) para a otimizacao da operacao de uma microrrede com o objetivo de reduzir o pico de demanda da rede eletrica principal, a qual esta conectada. A microrrede considerada neste trabalho e composta por um agrupamento de cargas definido, um sistema de geracao solar com 200kWp de potencia instalada e um sistema de armazenamento com baterias de ions de litio de 250kW de potencia e 560kWh de capacidade total. A formulacao do problema de otimizacao e realizada utilizando a abordagem de programacao linear inteira mista. Neste contexto, o modelo de controle MPC e implementado considerando um horizonte de previsao de 24 horas, com o objetivo de determinar os niveis de potencia que o sistema de armazenamento deve fornecer ou absorver para garantir a operacao otima da microrrede. Com isso, para avaliar o desempenho do controle proposto sao realizadas simulacoes considerando os limites operacionais com diferentes curvas de geracao solar e condicoes iniciais para o estado de carga do sistema de armazenamento.

In-memory computing (IMC) is attracting interest for accelerating data-intensive computing tasks, such as artificial intelligence (AI), machine learning (ML), and scientific calculus. IMC is typically conducted in the analog domain in crosspoint arrays of resistive random access memory (RRAM) devices or memristors. However, the precision of analog operations can be hindered by various sources of noise, such as the nonlinearity of the circuit components and the programming variations due to stuck devices and stochastic switching. Here we demonstrate high-precision IMC by a custom program-verify algorithm that uses redundancy to limit the impact of stuck devices and analog slicing to encode the analog programming error in a separate memory cell. The PageRank problem, consisting of the calculation of the principal eigenvector, is shown as a reference problem, adopting a fully integrated RRAM circuit. We extend these results to also include a convolutional neural network (CNN). We demonstrate a computing accuracy of 6.7 equivalent number of bits (ENOBs). Finally, we compare our results to the solution of the same problem by a static random access memory (SRAM)-based IMC, showcasing an advantage for the RRAM implementation in terms of energy efficiency and scaling.

Arm processors have been explored in HPC for several years, however there has not yet been a demonstration of viability for supporting large-scale production workloads. In this paper, we offer a retrospective on the process of bringing up Astra, the first Petascale supercomputer based on 64-bit Arm processors, and validating its ability to run production HPC applications. Through this process several immature technology gaps were addressed, including software stack enablement, Linux bugs at scale, thermal management issues, power management capabilities, and advanced container support. From this experience, several lessons learned are formulated that contributed to the successful deployment of Astra. These insights can be helpful to accelerate deploying and maturing other first-seen HPC technologies. With Astra now supporting many users running a diverse set of production applications at multi-thousand node scales, we believe this constitutes strong supporting evidence that Arm is a viable technology for even the largest-scale supercomputer deployments.

Neuronal activity of recurrent neural networks (RNNs) experimentally observed in the hippocampus is widely believed to play a key role for mammalian ability to associate concepts and make decisions. For this reason, RNNs have rapidly gained strong interest as computational enabler of brain-inspired cognitive functions in hardware. From the technology viewpoint, nonvolatile memory devices such as phase change memory (PCM) and resistive switching memory (RRAM) have become a key asset to allow for high synaptic density and biorealistic cognitive functionality. In this work, we demonstrate for the first time associative learning and decision making in a hardware Hopfield RNN with 6 spiking neurons and PCM synapses via storage, recall and competition of attractor states. We also experimentally demonstrate the solution of a constraint satisfaction problem (CSP) namely a Sudoku with size 2×2 in hardware and 9×9 in simulation. These results support spiking RNNs with PCM devices for the implementation of decision making capabilities in hardware neuromorphic systems.

Brain-inspired neuromorphic engineering aims at designing networks capable of learning from their own experience, in terms of both plasticity and stability. In biology, homeostatic scaling can regulate the frequency of neural processing in the brain and enable efficient synaptic learning activity. Implementing homeostatic regulation into hardware neural networks can thus enable stable, energy-efficient learning. Here, we present a novel artificial neuron based on phase change memory (PCM) devices capable of homeostatic regulation and power saving via self-adaptive threshold control. We experimentally show that this mechanism optimizes multi-pattern learning of the Fashion-MNIST dataset with asynchronous spike-timing-dependent plasticity (STDP). The PCM-based adaptive threshold is shown to act as a spike-frequency modulator of the whole neural network, giving robustness to the system against external perturbations. This work highlights the suitability of PCM devices for the optimization of synaptic dynamics and the implementation of brain-inspired neuromorphic circuits for cognitive agents and edge computing.

Thanks to the high parallelism endowed by physical rules, in-memory computing with crosspoint resistive memory arrays has been applied to accelerate typical dataintensive tasks such as the training and inference of deep learning. Recently, it has been shown that a crosspoint resistive switching memory (RRAM) circuit with a feedback configuration can be used to solve linear systems, compute eigenvectors, and rank webpages in just one step. Here, we demonstrate the PageRank with a real database (the Harvard500) together with an 8-level RRAM model that is based on experimental measurements, including the max/min conductance ratio, the high conductance range and the standard deviation of each level. By using a verify algorithm for the RRAM device programming, the PageRank result from the crosspoint circuit shows a cosine similarity of 93.5% with respect to the floating-point solution. With more discrete conductance levels and a broader high conductance range in the RRAM model, a better performance of cosine similarity up to 97% can be achieved. This work supports the feasibility of in-memory PageRank with realistic RRAM devices for real-world networks.

This paper introduces the setup of a Distributed Generation Microgrid (DGM) focused onto research on monitoring (electrical and environmental), controling and operating microgrids. This network is located at the Polytech Center Campus of the Federal University of Parana (UFPR), in Curitiba, Brazil. It consists of nine 13.8 kV feeders, three Distributed Generation (DG) sources and is connected to the main utility through a 69 kV distribution substation of the state electricity company named as Copel DIS. In addition to the electrical configuration, all components of the microgrid are presented, such as power generation, electrical and environmental meters, $\mu \mathrm{PMU}$ and the system monitoring computing environment.

This work describes the motivation and methodology of a first-of-its-kind global survey of HPC centers actively employing Energy and Power Aware Scheduling and Resource Management solutions for their production systems. The Energy-Efficient High-Performance-Computing Working-Group (EE HPC WG) Energy and Power Aware Job Scheduling and Resource Management (EPA JSRM) team conducted comprehensive interviews over the course of 2016 and 2017. In this work, we present the selection of participating sites, the motivation behind the survey, a detailed description of the questionnaire, and illustrate why getting a global view of the ongoing efforts is a major step towards more efficient systems. Job Scheduling and Resource Management is being tackled using new approaches regarding Power and Energy and has important implications for achievable center strategies. With this survey, we are laying foundations necessary to give insights in how problems and respective solutions are approached across sites and centers to allow to identify differences, similarities, solutions, and possible technology transfer across sites and centers. Upcoming work will focus on the survey responses and the analysis thereof. At the point of writing, the EPA JSRM team is in the major analysis phase of the centers' responses. By splitting the work in this fashion we achieve increased clarity in presentation and have the opportunity to generate more detailed analysis in benevolence of the community and reader.

The in-memory solution of linear systems with analog resistive switching memory in one computational step has been recently reported. In this work, we investigate the time complexity of solving linear systems with the circuit, based on the feedback theory of amplifiers. The result shows that the computing time is explicitly independent on the problem size N, rather it is dominated by the minimal eigenvalue of an associated matrix. By addressing the Toeplitz matrix and the Wishart matrix, we show that the computing time increases with log(N) or N1/2, respectively, thus indicating a significant speed-up of in-memory computing over classical digital computing for solving linear systems. For sparse positive-definite matrix that is targeted by a quantum computing algorithm, the in-memory computing circuit also shows a computing time superiority. These results support in-memory computing as a strong candidate for fast and energy-efficient accelerators of big data analytics and machine learning.

Neuromorphic computing has emerged as a promising approach for autonomous systems able to learn, adapt, and interact in real time with the environment. To build neuromorphic hardware, the recent development of novel material-based devices such as resistive switching memory (RRAM) has shown to be crucial since this class of devices offers the unique advantage to implement neuron and synaptic functions in silico by device physics, thus avoiding bulky circuits and very complex algorithms. In this work, we first explore volatile switching behaviour of RRAM devices, investigating their ability to capture short-term plasticity (STP) and short-term memory (STM) functionalities. Then, we characterise a volatile RRAM synapse, discussing its potential use in a spiking neural network for speech recognition applications.

This paper presents the results of an ongoing project involving the monitoring of micro phasor measurement units (micro-PMU) at Universidade Federal do Parana (UFPR). The infrastructure for receiving, processing and storing data from micro-PMUs, energy meters and power quality analysers was deployed. Free software were tested for data storage and visualization. We modified an existing open-source Energy Monitoring System (EMS) for proper use with PMUs. The software native communication protocol was adapted from hypertext protocol (HTTP) to direct reception of user datagram protocol (UDP) in IEEE Std. C37.118.2-2011 format to receive micro-PMUs transmission at 120 phasor per second. We modified data storage format to efficiently deal with time information allowing reduction of 60% of storage space in comparison to commonly used phasor data concentrator (openPDC).

The integration of renewable energy sources coordinated with the use of energy storage systems to provide power for a local grid is the main target for microgrids. Microgrids allow better integration of renewable sources, as well as allow adequate management of the storage elements, which bring improvements in power quality of the electrical systems. This paper presents the simulation results of the operation and control of a microgrid consisting of a photovoltaic generation system with energy storage (batteries) and the load in a distribution system. This work is part of the R&D project (Copel, 2016), whose objective is the development of a control system for the management of energy resources and loads of the consumer in the context of intelligent microgrids, as support to the integration of distributed generation. The management method is based on the construction of an optimal control algorithm and a hierarchical control structure of microgrids.

Electric power management has become a strong field of research and development in recent times. Most of the research is related to the so-called Smart Grids, which use information technology to increase the efficiency, reliability and sustainability of the system. In this paper, one of the available management tools, VOLTTRON, a multi-agent system developed by the United States Department of Energy, will be evaluated, along with the OpenADR communication standard. It presents simulated and practical implementations of the Strategic Project between the COPEL Distribution and the Federal University of Santa Maria which deals with technical and commercial arrangements for the insertion of energy storage systems in the Brazilian electrical system.

In this work a Mixed Integer Linear Programming (MILP) approach is proposed to model and optimize the operation of islanded microgrids. The objective is to attend the consumers power demand guaranteeing service quality requirements and considering battery operation costs. A novel formulation is proposed using a MILP approach to model complex penalization polices for energy supply interruption. A case study of a Brazilian utility in the context of local polices is presented. The obtained result shows this approach as a promising solution feasible to be integrated in Energy Management Systems.

The high performance computing industry is undergoing a period of substantial change. Not least because of fabrication and lithographic challenges in the manufacturing of next-generation processors. As such challenges mount, the industry is looking to generate higher performance from additional functionality in the micro-architecture space as well as a greater emphasis on efficiency in the design of networkon-chip resources and memory subsystems. Such variation in design opens opportunities for new entrants in the data center and server markets where varying compute-to-memory ratios can present end users with more efficient node designs for particular workloads. In this paper we compare the recently released Marvell ThunderX2 Arm processor - arguably the first high-performance computing capable Arm design available in the marketplace. We perform a set of micro-benchmarking and mini-application evaluation on the ThunderX2 comparing it with Intel’s Haswell and Skylake Xeon server parts commonly used in contemporary HPC designs. Our findings show that no one processor performs the best across all benchmarks, but that the ThunderX2 excels in areas demanding high memory bandwidth due to the provisioning of more memory channels in its design. We conclude that the ThunderX2 is a serious contender in the HPC server segment and has the potential to offer supercomputing sites with a viable high-performance alternative to existing designs from established industry players.

In the era of big data, there is a strong urge for novel methodologies of computing large amount of unstructured data with short latency and low power. Toward this goal, in-memory computing has emerged as a paradigm shift to enable processing the data directly within or close to the memory, thus overcoming the memory wall typical of the von Neumann architecture [1]. Computation within resistive memory devices, such as resistive switching memory (RRAM) and phase change memory (PCM) has the additional advantage of physical computing, where data are processed via fundamental physical laws, such as the Ohm's law and the Kirchhoff's law, thus enabling a massive parallelism and the consequent acceleration of computational tasks, such as the matrix-vector multiplication (MVM). In this work, we will demonstrate an extreme speedup for solving matrix algebra problems, such as solution of linear systems or calculation of eigenvectors, via MVM in crosspoint arrays of resistive memory devices with feedback configuration [2].

This paper demonstrates a monolithic surface acoustic wave amplifier fabricated by state-of-the-art heterogenous integration of a IH-V InGaAs-based epitaxial material stack and LiNb03. Due to the superior properties of the materials employed, we observe electron gain and also non-reciprocal gain in excess of 30dB with reduced power consumption. Additionally, we present a framework for performance optimization as a function of material parameters for a targeted gain. This platform enables further advances in active and non-reciprocal piezoelectric acoustic devices.

Monitoring of High Performance Computing (HPC) platforms is critical to successful operations, can provide insights into performance-impacting conditions, and can inform methodologies for improving science throughput. However, monitoring systems are not generally considered core capabilities in system requirements specifications nor in vendor development strategies. In this paper we present work performed at a number of large-scale HPC sites towards developing monitoring capabilities that fill current gaps in ease of problem identification and root cause discovery. We also present our collective views, based on the experiences presented, on needs and requirements for enabling development by vendors or users of effective sharable end-to-end monitoring capabilities.

We demonstrate thinned resonant longwave infrared detectors with quantum efficiencies of over 60% in the longwave infrared. This improvement over unthinned detectors is made possible by a nanoantenna that confines the incident optical energy in a reduced volume compared to traditional detector architectures.

Electric Vehicles (EV) are every day more and more important and diffuse in all day life. The major drawbacks of the present EVs are the long charging times and mechanical hassles with charging cables. The wireless battery charging is an effective solution to overcome these issues in particular if it is performed also during momentarily stopping phases of the vehicle (e.g. at traffic light). This paper investigates, by means of simulations, a power transfer system for a quasi-dynamic Wireless Power Transfer (WPT) System for EV batteries charging.

Recent development of aintegrated micro-scale hybrid PV/CPV approach is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The development of the firstgeneration prototype module based on the WPV concept is described. Initial outdoor module characterization results will also be discussed. The WPV approach is experimentally shown to achieve over 100% improvement on the concentration-acceptance-angle product (CAP), using the wafer-embedded non-imaging micro-concentrating elements. The wafer-embedded-features lead to significantly reduced module material and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture compatible with commercial flat panel infrastructures. The performance of the PV/CPV hybrid architecture is projected to illustrate its potential for cost-effective collection of both direct and diffuse sunlight, thereby extending the geographic and market domains for cost-effective PV system deployment. Our outdoor testing results on diffuse light collector in Cambridge, MA, USA indicate strong forward scattering effect of the diffuse light, which consequently can be utilized to design efficient diffuse concentrators to further reduce the cost of the Si cell. Leveraging low-cost micro-fabrication and high-level integration techniques, the micro-scale PV/CPV hybrid approach effectively combines the high performance of multijunction solar cells and the low costs of flat-plate Si PV systems.

Large-scale HPC systems increasingly incorporate sophisticated power management control mechanisms. While these mechanisms are potentially useful for performing energy and/or power-aware job scheduling and resource management (EPA JSRM), greater understanding of their operation and performance impact on real-world applications is required before they can be applied effectively in practice. In this paper, we compare static p-state control to static node-level power cap control on a Cray XC system. Empirical experiments are performed to evaluate node-to-node performance and power usage variability for the two mechanisms. We find that static p-state control produces more predictable and higher performance characteristics than static node-level power cap control at a given power level. However, this performance benefit is at the cost of less predictable power usage. Static node-level power cap control produces predictable power usage but with more variable performance characteristics. Our results are not intended to show that one mechanism is better than the other. Rather, our results demonstrate that the mechanisms are complementary to one another and highlight their potential for combined use in achieving effective EPA JSRM solutions.

Emerging memory devices such as resistive switching memory (RRAM) and phase change memory (PCM) are gaining interest as future synapses for smart neuromorphic systems, capable of learning and inference similar to the human brain. Developing neuromorphic systems with emerging memory technologies requires accurate co-design of devices, synapses, and neural networks, aiming at the replication of the fundamental learning processes in the human brain, such as spike-timing dependent plasticity (STDP) and spike-rate dependent plasticity (SRDP). This work addresses the development of RRAM synapses for unsupervised learning via STDP. This learning scheme is implemented in a simple one-transistor/one-resistor (1T1R) structure capable of long term potentiation and depression with standard memory-grade RRAM devices. 1T1R synapses are implemented in a spiking neural network (SNN) with feedforward architecture, allowing for the hardware demonstration of unsupervised learning. Recurrent SNNs employing the same fundamental STDP rule are then addressed by simulation of associative learning, pattern reconstruction, and recall of spatiotemporal sequences.