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The rapid growth of data center, ubiquitous cloud computing, and mobile gadgets has made flash memory one of the major semiconductor markets. The booming request of flash memory has not only brought substantial economic and societal benefit but led to growing power consumption. The operation voltage of existent flash memory is in the range of 15–17 V which still has much room to be reduced to save power while ensuring environmental sustainability. To enable flash memory at lower voltage, developing innovative materials and structures is a prerequisite. Recently, crystalline oxide is extensively developed as a novel charge trapping layer (CTL) and holds the prospect of becoming a promising candidate for memory applications by demonstrating operation voltage lower than 10 V. In this paper, how crystalline oxide in the form of high-k dielectric and semiconductor material can be employed in flash memory as the CTL to reduce the operation voltage and the mechanism to achieve this goal are reviewed. From the good memory performance in terms of a large memory window of 1.5 V by programming/erasing at voltage lower than 10 V for 1 ms, endurance more than $10^{5}$ operation cycles, desirable retention at 85 °C, employing crystalline oxide as the CTL has ushered in a new field to implement green flash memory devices.

In this work we present a modeling study of a conceptual low power non-volatile memory cell based on inorganic molecular metal oxide clusters (polyoxometalates (POM)) as a storage media embedded in the gate dielectric of a Fully Depleted SOI (FD SOI) with reduced statistical variability. The simulations were carried out using a multi-physics simulation framework, which allows us to evaluate the variability in the programming window of the molecular based flash cell with an 18 nm gate length. We have focused our study on the threshold voltage variability influenced by random dopant fluctuations and random special fluctuations of the molecules in the floating gate of the flash-cell. Our simulation framework and conclusions can be applied not only to POM-based flash cell but also to flash cells based on alternative molecules used as a storage media.

A multiple-stage simulation procedure identifies, for the first time, the location of secondary electrons that very efficiently produce gate currents in flash EEPROMs. The simulation method incorporates both electron and hole Monte Carlo analysis to calculate this secondary electron gate current without introducing additional fitting parameters. (I/sub g//I/sub d/) continues to increase for smaller channel length (50/spl times/ from L/sub g/-03.39 to 0.12 /spl mu/m) and higher substrate doping (more than 6/spl times/ when doubled) in scaled, low-power flash memory.