72 results on '"Radu, Iuliana"'
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2. Contact Optimization Through Annealing and Edge Functionalization Towards 2D TMD Nanosheet Devices
3. Barrier Booster for Remote Extension Doping and its DTCO for 1D & 2D FETs
4. Low N-Type Contact Resistance to Carbon Nanotubes in Highly Scaled Contacts through Dielectric Doping
5. Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel
6. High-Endurance MoS2 FeFET with Operating Voltage Fess Than IV for eNVM in Scaled CMOS Technologies
7. Monolayer-MoS2 Stacked Nanosheet Channel with C-type Metal Contact
8. First Demonstration of GAA Monolayer-MoS2 Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length
9. Computational Screening and Multiscale Simulation of Barrier-Free Contacts for 2D Semiconductor pFETs
10. High-Performance Monolayer WSe2 p/n FETs via Antimony-Platinum Modulated Contact Technology towards 2D CMOS Electronics
11. pMOSFET with CVD-grown 2D semiconductor channel enabled by ultra-thin and fab-compatible spacer doping
12. Nearly Ideal Subthreshold Swing in Monolayer MoS₂ Top-Gate nFETs with Scaled EOT of 1 nm
13. Comprehensive Physics Based TCAD Model for 2D MX2 Channel Transistors
14. Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS
15. Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor
16. Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements
17. Dual gate synthetic MoS2 MOSFETs with 4.56µF/cm2 channel capacitance, 320µS/µm Gm and 420 µA/µm Id at 1V Vd/100nm Lg
18. Scaling of double-gated WS2 FETs to sub-5nm physical gate length fabricated in a 300mm FAB
19. Superior electrostatic control in uniform monolayer MoS2 scaled transistors via in-situ surface smoothening
20. Contact Interface Characterization of Graphene contacted MoS2 FETs
21. Impact of Metal Hybridization on Contact Resistance and Leakage Current of Carbon Nanotube Transistors.
22. ALD Encapsulation of CVD WS2 for Stable and High-Performance FET Devices
23. Circuit models for the co-simulation of superconducting quantum computing systems
24. Dual gate synthetic WS2 MOSFETs with 120μS/μm Gm 2.7μF/cm2 capacitance and ambipolar channel
25. Sources of variability in scaled MoS2 FETs
26. Efficient Modeling of Charge Trapping at Cryogenic Temperatures—Part I: Theory.
27. Efficient Modeling of Charge Trapping at Cryogenic Temperatures—Part II: Experimental.
28. Ultra-scaled MOCVD MoS2 MOSFETs with 42nm contact pitch and 250µA/µm drain current
29. The Growing Application Field of Laser Debonding: From Advanced Packaging to Future Nanoelectronics
30. Device and Circuit Level Gate Configuration Optimization for 2D Material Field-Effect Transistors
31. All-Electrical Control of Scaled Spin Logic Devices Based on Domain Wall Motion.
32. First experimental demonstration of a scalable linear majority gate based on spin waves
33. An Integrated Silicon MOS Single-Electron Transistor Charge Sensor for Spin-Based Quantum Information Processing.
34. Spin-based majority gates for logic applications
35. Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors
36. Interconnect-Device Co-Optimization for Field-Effect Transistors with Two-Dimensional Materials
37. Towards high-performance polarity-controllable FETs with 2D materials
38. Material selection and device design guidelines for two-dimensional materials based TFETs
39. Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures
40. Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective
41. Atom-thick transistors.
42. Performance Comparison of s-Si, In0.53Ga0.47As, Monolayer BP- and WS2-Based n-MOSFETs for Future Technology Nodes—Part II: Circuit-Level Comparison.
43. Performance Comparison of s-Si, In0.53Ga0.47As, Monolayer BP, and WS2-Based n-MOSFETs for Future Technology Nodes—Part I: Device-Level Comparison.
44. Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI.
45. The Role of Nonidealities in the Scaling of MoS2 FETs.
46. Microwave Characterization of Ba-Substituted PZT and ZnO Thin Films.
47. Improving MOCVD MoS2 Electrical Performance: Impact of Minimized Water and Air Exposure Conditions.
48. Design and benchmarking of hybrid CMOS-Spin Wave Device Circuits compared to 10nm CMOS
49. Area and routing efficiency of SWD circuits compared to advanced CMOS
50. FETs on 2-D Materials: Deconvolution of the Channel and Contact Characteristics by Four-Terminal Resistance Measurements on WSe2 Transistors.
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