138 results on '"Raghavan, Praveen"'
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2. Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching
3. Patterning Aware Design Optimization of Selective Etching in N5 and Beyond
4. Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7
5. Material selection and device design guidelines for two-dimensional materials based TFETs
6. Dedicated technology threshold voltage tuning for 6T SRAM beyond N7
7. Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective
8. Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI.
9. Architectures for cognitive radio testbeds and demonstrators - An overview
10. Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability
11. Power noise in 14, 10, and 7 nm FinFET CMOS technologies
12. Comparative BTI analysis for various sense amplifier designs
13. The impact of process variation and stochastic aging in nanoscale VLSI
14. Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios
15. STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance
16. Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power
17. Design and benchmarking of hybrid CMOS-Spin Wave Device Circuits compared to 10nm CMOS
18. Modeling FinFET metal gate stack resistance for 14nm node and beyond
19. Impact of device and interconnect process variability on clock distribution
20. Area and routing efficiency of SWD circuits compared to advanced CMOS
21. Variability of quadruple-patterning interconnect processes
22. Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier
23. Integral impact of BTI and voltage temperature variation on SRAM sense amplifier
24. Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node
25. Device/system performance modeling of stacked lateral NWFET logic.
26. MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts.
27. Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node.
28. Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier.
29. A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less.
30. NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes
31. Majority Logic Synthesis for Spin Wave Technology
32. System-level assessment and area evaluation of Spin Wave logic circuits
33. 2D vs 3D integration: Architecture-technology co-design for future mobile MPSoC platforms
34. Interconnects scaling challenge for sub-20nm spin torque transfer magnetic random access memory technology
35. Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology
36. A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication
37. Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity
38. A C-programmable baseband processor with inner modem implementations for LTE Cat-4/5/7 and Gbps 80MHz 4×4 802.11ac (invited)
39. An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard
40. Energy impact in the design space exploration of loop buffer schemes in embedded systems
41. Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design
42. CMOS low-power transceivers for 60GHz multi Gbit/s communications
43. Impact of interconnect multiple-patterning variability on SRAMs.
44. STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance.
45. Bias temperature instability analysis in SRAM decoder
46. Data memory optimization in LTE downlink
47. Impact of Wire Geometry on Interconnect RC and Circuit Delay.
48. Benchmarking of MoS2 FETs With Multigate Si-FET Options for 5 nm and Beyond.
49. Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node.
50. A Scalable MIMO Detector Processor With Near-ASIC Energy Efficiency.
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