135 results on '"Rosenbaum, Elyse"'
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2. Thermal-Aware SoC Macro Placement and Multi-chip Module Design Optimization with Bayesian Optimization
3. Collector Engineering of ESD PNP in BCD Technologies
4. Optimization of SCR for High-Speed Digital and RF Applications in 45-nm SOI CMOS Technology
5. Semantic Autoencoder for Modeling BEOL and MOL Dielectric Lifetime Distributions
6. A Methodology to Optimize the Number and Placement of Decoupling Capacitors in a Multilevel Power Delivery Network
7. A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology
8. Neural Ordinary Differential Equation Models of Circuits: Capabilities and Pitfalls.
9. Neural Networks for Transient Modeling of Circuits : Invited Paper
10. Considerations in High Voltage Lateral ESD PNP Design
11. Compact Model of ESD Diode Suitable for Subnanosecond Switching Transients
12. An Interpretable Predictive Model for Early Detection of Hardware Failure
13. Sub-nanosecond Reverse Recovery Measurement for ESD Devices
14. Statistical Learning of IC Models for System-Level ESD Simulation.
15. Decomposition Method for Event-Detection State Vector Simulation of Switched-Mode Power Supplies
16. Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors
17. Discrete-Time Large-Signal Modeling and Numerical Methods for Flyback Converters
18. Enhanced IC Modeling Methodology for System-level ESD Simulation
19. Latch-up Model of Non-collinear PNPN Structures
20. Hardware and Software Combined Detection of SystemLevel ESD-Induced Soft Failures
21. Special Issue on Reliability.
22. Stochastic modeling of air electrostatic discharge parameters
23. Chip-Level ESD-induced noise on internally and externally regulated power supplies
24. On-Chip monitors of supply noise generated by system-level ESD
25. Analysis and Design of Integrated Voltage Regulators for Supply Noise Rejection During System-Level ESD.
26. Application level investigation of system-level ESD-induced soft failures
27. 2014 Best Paper and Best Student Paper Award
28. Case study of DPI robustness of a MOS-SCR structure for automotive applications
29. Measurement and Simulation of On-Chip Supply Noise Induced by System-Level ESD.
30. Improving the long pulse width failure current of NPN in BiCMOS technology
31. Experimental study of supply voltage stability during ESD
32. Tutorial I: Influence of IC packaging technology on ESD robustness of components
33. CDM-reliable T-coil techniques for high-speed wireline receivers
34. 2013 Best Student Paper Award
35. Practical methodology for the extraction of SEED models
36. Current challenges in component-level and system-level ESD simulation
37. Improved GGSCR layout for overshoot reduction
38. Soft-Failures Induced by System-Level ESD.
39. ESD Self-Protection of High-Speed Transceivers Using Adaptive Active Bias Conditioning.
40. CDM-Reliable T-Coil Techniques for a 25-Gb/s Wireline Receiver Front-End.
41. S-parameter based modeling of system-level ESD test bed.
42. Fast circuit simulator for transient analysis of CDM ESD.
43. Full-Component Modeling and Simulation of Charged Device Model ESD.
44. Physical Basis for CMOS SCR Compact Models.
45. Charged Device Model Reliability of Three-Dimensional Integrated Circuits.
46. Analysis of Active-Clamp Response to Power-On ESD: Power Supply Integrity and Performance Tradeoffs.
47. A co-optimization methodology on ESD robustness and functionality for pad-ring circuitry.
48. A mechanism for logic upset induced by power-on ESD.
49. Theory of active clamp response to power-on ESD and implications for power supply integrity.
50. Custom test chip for system-level ESD investigations.
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