156 results on '"Rossi, Davide"'
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2. PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge
3. A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks
4. Cyber Security aboard Micro Aerial Vehicles: An OpenTitan-based Visual Communication Use Case
5. TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes
6. HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
7. 22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing
8. Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training
9. Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs
10. GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors
11. Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference
12. Worldwide Gender Differences in Public Code Contributions and how they have been affected by the COVID-19 pandemic
13. RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs
14. Hardware-In-The Loop Emulation for Agile Co-Design of Parallel Ultra-Low Power IoT Processors
15. A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
16. End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet?
17. XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V based IoT End Nodes
18. A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics.
19. 4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
20. An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes
21. Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
22. Neuro-PULP: A Paradigm Shift Towards Fully Programmable Platforms for Neural Interfaces
23. A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference
24. Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster
25. TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE
26. XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions
27. Pushing On-chip Memories Beyond Reliability Boundaries in Micropower Machine Learning Applications
28. PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters
29. A PULP-based Parallel Power Controller for Future Exascale Systems
30. An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks
31. Resilient Reactive Systems Based on Runtime Semantic Models
32. A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS.
33. DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs.
34. Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation.
35. Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes.
36. Reducing Crossbar Costs in the Match-Action Pipeline
37. Hardware-Accelerated Energy-Efficient Synchronization and Communication for Ultra-Low-Power Tightly Coupled Clusters
38. Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA
39. Quentin: an Ultra-Low-Power PULPissimo SoC in 22nm FDX
40. Independent Body-Biasing of P-N Transistors in an 28nm UTBB FD-SOI ULP Near-Threshold Multi-Core Cluster
41. Low-latency Packet Parsing in Software Defined Networks
42. Modular Design and Optimization of Biomedical Applications for Ultralow Power Heterogeneous Platforms.
43. Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge.
44. BioWolf: A Sub-10-mW 8-Channel Advanced Brain–Computer Interface Platform With a Nine-Core Processor and BLE Connectivity.
45. Mr. Wolf: A 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for IOT Edge Processing
46. Hyperdrive: A Systolically Scalable Binary-Weight CNN Inference Engine for mW IoT End-Nodes
47. GAP-8: A RISC-V SoC for AI at the Edge of the IoT
48. Compressed Sensing Based Seizure Detection for an Ultra Low Power Multi-core Architecture
49. An Explicitly Parallel Architecture for Packet Parsing in Software Defined Networks
50. PULP-HD: Accelerating Brain-Inspired High-Dimensional Computing on a Parallel Ultra-Low Power Platform
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