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Mobile systems are facing a number of application vulnerabilities that can be combined together and utilized to penetrate systems with devastating impact. When assessing the overall security of a mobile system, it is important to assess the security risks posed by each mobile applications (apps), thus gaining a stronger understanding of any vulnerabilities present. This paper aims at developing a three-layer framework that assesses the potential risks which apps introduce within the Android mobile systems. A Bayesian risk graphical model is proposed to evaluate risk propagation in a layered risk architecture. By integrating static analysis, dynamic analysis, and behavior analysis in a hierarchical framework, the risks and their propagation through each layer are well modeled by the Bayesian risk graph, which can quantitatively analyze risks faced to both apps and mobile systems. The proposed hierarchical Bayesian risk graph model offers a novel way to investigate the security risks in mobile environment and enables users and administrators to evaluate the potential risks. This strategy allows to strengthen both app security as well as the security of the entire system. [ABSTRACT FROM PUBLISHER]

A deep metastability measurement scheme has been implemented on chip using digital circuits with 0.18 μm technology. Compared with previous off-chip implementations using analog circuits, the on-chip implementation allows integration of both the synchronizer circuits and the measurement method, and eliminates high-speed off-chip paths which are a source of inaccuracy. It also makes control at the picosecond level easier because of the inherent stability of digital integrating counters and digital delay lines. Our results show that the digital delay line used to adjust the data to clock times is controllable to an increment of 0.1 ps, and the input time distribution is 5.2 ps compared with 7.6 ps for the analog version. Because of the use of high and too counters, we can control the ratio of high to too outputs so that the actual input distribution can be measured to within better than 1 ps. The metastability time constant τ has been measured down to 10-17 s which corresponds to an mean time between failures (MTBF) of 100 seconds in an experimental time of 10 minutes and can he extended to a lower level by increasing the measurement time. Our results also show that a new synchronizer circuit designed for robustness to variation in Vdd performed at least as well as the Jamb Latch at all values of Vdd, and is more than 20% faster when Vdd was reduced by 25%. [ABSTRACT FROM AUTHOR]

Present measurement techniques do not allow synchronizer reliability to be measured in the region of most interest, that is, beyond the first half cycle of the synchronizer clock. We describe methods of extending the measurement range, in which the number of metastable events generated is increased by four orders of magnitude and events with long metastable times are selected from the large number of more normal events. The relationship found between input times and the resulting output times is dependent on accurate measurement of input time distributions with deviations of less than 10 ps. We show how the distribution of D to clock times at the input can be characterized in the presence of noise and how predictions of failure rates for long synchronizer times can be made. Anomalies such as the increased failure rates in a master-slave synchronizer produced by the back edge of the clock are explained and demonstrated. [ABSTRACT FROM AUTHOR]