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Cotton lint samples drawn from densely packed bales are required to be well opened and cleaned before being used for fibre quality assessment using modern testing equipment. Importance of proper opening of lint samples introduced into the porosity chamber for measurement of fibre fineness (micronaire) is well recognized to ensure not only correct micronaire but also strength values. If lint samples are tested as such without any opening and cleaning, there is every possibility of variations in the micronaire reading from the actual value. In this paper, performance of the two equipments namely trash analyzer and opener blender has been analyzed for opening of cotton lint samples to ensure accurate and precise measurement of fibre fineness using High Volume Instrument. It was observed that while both equipments gave similar quality of opening, the capacity of trash analyzer was nearly double due to its larger size when compared to opener blender.

CPD cathode, made out of tungsten wire, using active sintering resulted in uniform and two-fold emission as compared to B-type cathode. Studies on wire diameter using MATLAB code suggests that 20 μm diameter provides optimum barium coverage. Detailed experimental results will be presented. A conventional dispenser cathode has an emitting button, made out of porous tungsten. The pores are distributed in random sizes and shapes across the surface. As a result the barium diffusion from bulk to the pore end and the subsequent migration into the inter-pore region are not uniform all across the surface, due to which the emission uniformity is affected. Figure 1. SEM image of CP pellet A cathode wherein the distribution and size of the pores can be directly controlled would represent a controlled porosity dispenser (CPD) cathode. One of the techniques to fabricate a CPD cathode pellet is by slicing a pellet out of sintered bunch of tungsten (W) wires [1]. A simple technique has been developed by us [2] to fabricate the pellet out of “activated sintered bunch of tungsten (W) wires”. In this approach the activation energy for sintering is lowered by an addition of a small amount of active material thereby avoiding the need to reach elevated temperatures. A compression fixture has been designed and fabricated to carry out sintering operation under pressure. The fabrication of CPD cathode assembly, mainly, involved: (a) making bunch, out of bits of W-wire of diameter 50 μm and compressing under hot condition, (b) machining of bunch using wire cutting to obtain pellets, (c) vacuum firing of pellets to remove the excess active material, (d) impregnating the pellets with barium-calcium-aluminates in the ratio of 4:1:1, and (e) integration of the impregnated pellets with potted heater assembly using laser tagging. Figure 2. Pulsed I-V characteristics of CPD Cathode The SEM image the cathode pellet is shown in Fig. 1.The pores have a triangular geometry with hexagonal distribution 978-1-4799-5772-9/14/$31.00 ©2014 IEEE around the circumference of each wire. The average pore size is found to be about 11μm when the triangle is replaced with an effective circle of same area. The cathodes were tested in an analytical system comprising of: (a) anode for emission measurements and (b) Auger electron spectroscopy (AES) system for surface analysis. The I-V plots are shown in Fig. 2. The emission is about twice that of a conventional B-type cathode for the same temperatures. This is attributed to high Ba/W and O/W ratios on the surface as compared to those of a B-type. Miram curves generated, out of pulse emission data, exhibited a better temperature limited and fully space charge limited (TL-FSCL) transition at lower FSCL current densities and, also, a lower patchiness of emission as compared to those of a B-type. Figure 3. Histograms representing percentage area (of different coverage) with wire radius A code “CPD CALCULATOR” which is a graphical user interface (GUI) has been developed using MATLAB software, incorporating the diffusion dynamics, to graphically appreciate the steady state Ba spread. These studies show that the barium coverage falls exponentially from the pore edge [3]. To obtain a large fraction of area with the required minimum coverage (θ), the inter-pore distance should be comparable to the diffusion length. A model has been developed to estimate the optimum wire size for a good performance. The results are shown in Fig. 3 in the form of histogram. It can be seen that there is no added advantage if we go for wire size lower than that 20 μm. For wire size greater than 40 μm, though a large area is well covered (θ>0.7), the pore size would be greater than that of B-type, resulting in high evaporation.

Thermionic emission microscope (THEM) is an analytical research tool to study the emission uniformity of a thermionic cathode. In this paper, the design of electrostatic lens for a multi-beam cathode (MBC) has been given using 2-D TRAK and Omni-TRAK codes. The design of single beam lens system, available with us, containing a small cathode has been modified to study large size MBC using scaling laws. The present MBC contains 19 protruding buttons contributing to 19 beamlets whose image is projected onto the screen for study. The influence of various parameters such as protrusion, diameter of button, and their interspacing has been studied. The studies prove that THEM could be used as an effective tool for the characterization of MBC.

In the recent past, CMOS manufacturing technology has been downscaled successfully to create feature sizes below 100 nm. But with the predicted demise of Moore’s law, continued success of the electronic industry will increasingly depend on emerging non-silicon nanotechnologies. CMOS or not, affordable manufacturing of defect-free nanosystems seems unlikely. Besides manufacturing defects, various transient faults will affect these systems. Therefore, there is a need for developing computing systems that are tolerant to defects and faults. Although several methodologies have been published in the literature to design defect-and fault-tolerant nanoscale systems, there is a severe lack of CAD tools to aid the design and analysis of such systems. In this paper, we develop multiple methodologies and tools to (i) design fault-tolerant nanosystems on architectures based on different nanotechnologies, and (ii) quantitatively analyze the performance of such nanosystems in terms of reliability, area and delay.