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As silicon semiconductor device feature size scales down to the nanometer range, planar bulk CMOS design and fabrication encounter significant challenges nowadays. Carbon Nanotube Field Effect Transistor (CNTFET) has been introduced for high stability, high performance and low power SRAM cell design as an alternative material. Technology scaling demands a decrease in both V DD and V T to sustain historical delay reduction, while restraining active power dissipation. Scaling of V T however leads to substantial increase in the sub-threshold leakage power and is expected to become a considerable constituent of the total dissipated power. It has been observed that the stacking of two off devices has smaller leakage current than one off device. This paper proposes a SRAM cell circuit based on CNTFET that uses Forced Stack Technique to reduce leakage power. The advantage of this circuit compared to sleep-transistor technique is that it can save the state. This circuit is simulated using HSPICE with Stanford CNFET model at 32nm. The simulated results shows that this proposed Forced Stack CNTFET SRAM cell reduces a leakage-power by a significant amount compared to conventional 6T CNTFET SRAM cell with minimal Area and delay trade off.

The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube FETs (CNTFETs) are considered to be the possible “ beyond CMOS” device due to its 1-D transport properties that include low carrier scattering and ballistic transport. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.