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Random trapping and detrapping of charged carriers in the vicinity of gate oxide/Si interface has for long been considered as the dominant noise source in Si nanowire (SiNW) FET-based biochemical sensors. Here we extend our previous work presenting a Schottky junction tri-gate SiNWFETs (SJGFET) fabricated on a bonded silicon-on-insulator (SOI) substrate, aiming for ultra-low device noise generation. The SJGFET exhibits near-ideal gate coupling efficiency with a subthreshold swing of ~66 mV/dec. Its gate-referred voltage noise, Svg, are 1.2 × 10−10 and 1.1 × 10−11 V2 μm2/Hz at 1 and 10 Hz, respectively. These Svg values are significantly lower than that of previously reported FET-based sensors. More importantly, Svg of the SJGFET are below the reported voltage noise generated by the oxide/electrolyte sensing interface. Using our SJGFET as the signal transducer can greatly relieve the concern of the adverse effect from the intrinsic device noise in biochemical sensing applications. [ABSTRACT FROM AUTHOR]

This letter presents a systematic study of how the substrate bias (${V}_{\text {sub}}$) modulation affects the current-voltage (${I}$ - ${V}$) characteristics and low-frequency noise (LFN) of lateral bipolar junction transistors (LBJTs) fabricated on a silicon-on-insulator (SOI) substrate. The current gain ($\beta$) of npn LBJTs at low base voltage can be greatly improved by a positive ${V}_{\text {sub}}$ as a result of enhanced electron injection into the base near the buried oxide (BOX)/silicon interface. However, an excessive positive ${V}_{\text {sub}}$ may also adversely affect the LFN performance by amplifying the noise generated as a result of carrier trapping and detrapping at that interface. Our results provide a practical guideline for improving both $\beta $ and the overall noise performance when using our LBJT as a local signal amplifier. [ABSTRACT FROM AUTHOR]

Silicon nanowire (SiNW) field-effect transistors (SiNWFETs) are of great potential as a high-sensitivity charge sensor. The signal-to-noise ratio (SNR) of an SiNWFET sensor is ultimately limited by the intrinsic device noise generated by carrier trapping/detrapping processes at the gate oxide/silicon interface. This carrier trapping/detrapping-induced noise can be significantly reduced by replacing the noisy oxide/silicon interface with a Schottky junction gate (SJG) on the top of the SiNW. In this paper, we present a tri-SJG SiNWFET (Tri-SJGFET) with the SJG formed on both the top surface and the two sidewalls of the SiNW so as to enhance the gate control over the SiNW channel. Both experiment and simulation confirm that the additional sidewall gates in a narrow Tri-SJGFET indeed can confine the conduction path within the bulk of the SiNW channel away from the interfaces and significantly improve the immunity to the traps at the bottom buried oxide/silicon interface. Therefore, the optimal low-frequency noise performance can be achieved without the need for any substrate bias. This new gating structure holds promises for further development of robust SiNWFET-based charge sensors with low noise and low operation voltage. [ABSTRACT FROM AUTHOR]

Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau–Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies. [ABSTRACT FROM AUTHOR]

This paper presents a highly sensitive, energy efficient, and low-cost distributed methane (CH4) sensor system (DMSS) for continuous monitoring, detection, and localization of CH4 leaks in natural gas infrastructure, such as transmission and distribution pipelines, wells, and production pads. The CH4 sensing element, a key component of the DMSS, consists of a metal–oxide nanocrystal functionalized multi-walled carbon nanotube mesh, which, in comparison with the existing literature, shows stronger relative resistance change while interacting with lower parts per million concentration of CH4. A Gaussian plume triangulation algorithm has been developed for the DMSS. Given a geometric model of the surrounding environment, the algorithm can precisely detect and localize a CH4 leak as well as estimate its mass emission rate. A UV-based surface recovery technique making the sensor recover ten times faster than the reported ones is presented for the DMSS. A control algorithm based on the UV-accelerated recovery is developed, which facilitates faster leak detection. [ABSTRACT FROM PUBLISHER]

Transistor amplification properties of a three-leg spirofluorene-based molecule are investigated, and the transistor is shown to possess usable current, voltage, and power gain. Current gain is facilitated since the source-drain legs are conjugated, whereas the gate (control) leg is unconjugated and spatially orthogonal, and voltage gain is enhanced by the efficient quantum-mechanical coupling to the gate. Full quantum-mechanical calculations were done for all three electrodes, using the density functional formalism and a plane-wave decomposition of the wave functions. [ABSTRACT FROM PUBLISHER]

It has recently been suggested that ferroelectric (FE) negative capacitance effects can be used to achieve steep subthreshold slope field-effect transistors, which are greatly desired for reducing energy consumption in modern digital electronics. Here, we propose that this concept can be improved by the introduction of a very thin metal or metal-like layer (a quantum metal) between the FE and the semiconductor channel. We show how to design this layer so that it attenuates the polarization charge of the FE, applying an appropriate charge to the semiconductor, while at the same time presenting a relatively constant capacitance to the FE layer, as is needed to stabilize the negative capacitance regime. For homogeneous polarization, we estimate that this device (a QMFeFET) can have extremely steep subthreshold characteristics (2 mV/decade over 11 decades) and that its energy and delay performance are advantageous. [ABSTRACT FROM AUTHOR]

An experimental study is presented to probe the interface barriers of dopant-segregated silicide–Si diodes with internal photoemission. The spatial information of the interface dipoles, which is believed to be the cause of the effective Schottky barrier height (SBH) modification, is extracted from the field dependence of the barrier heights. A clear difference between the dopant segregation (DS) junctions and a pure Schottky junction is found: Boron DS modifies the effective SBH by forming a \p^+\- \n junction while arsenic DS forms a “Shannon” junction with a fully depleted 1.5-nm doping depth in front of the silicide. [ABSTRACT FROM AUTHOR]

Experimental-modeling investigation of the transient thermal crosstalk between the field-effect transistors implemented on a silicon-on-insulator substrate is reported. The measurements were performed using a high-speed electrical pulse—probe sampling technique, which allowed detection of thermally modulated subthreshold currents. The technique achieved a temperature resolution of ∼50 mK, a time resolution of 5 ns, and a temperature sensitivity of ∼0.6 μA/K. The finite-element method was used to solve the heat diffusion equation and to obtain the temperature profiles for the given device structures. The combined high-resolution experimental—simulation approach allowed the study of the thermal crosstalk between two adjacent devices and probe the local temperature at different locations of the structure. The effects of the interface quality, layer thickness, material selection, and interdevice spacing on the heat diffusion and device performance were investigated in detail. [ABSTRACT FROM AUTHOR]