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In order to model high-speed nonlinear circuits, recurrent neural network (RNN) has been widely used in computer-aided design (CAD) area to achieve high performance and fast models compared with the existing models. Despite their advantages, they still have challenges such as large training time and limited test accuracy. In this article, the batch normalization (BN) method is applied to deep RNN leading to a much shorter training time and more accurate models compared with the conventional RNN. The proposed BN-RNN method works by modifying the distribution of the internal nodes of a deep network in the training course as an internal auxiliary shift yielding a much faster training. Indeed, the internal covariance shift will be reduced and the training of deep neural networks will be accelerated via a normalization step applied to the layers of RNN. BN-RNN, moreover, has a beneficial effect on gradient flow through the grid by reducing the dependence of gradients on the scale of network parameters or their initial values. This provides a much better learning process without the risk of divergence. For verifying the proposed method, time-domain modeling of three high-speed nonlinear circuits operating at the GHz region is provided. Comparisons of the training and test errors between RNN and BN-RNN, and evaluation time comparisons between transistor level and the BN-RNN-based models for these circuits prove the higher speed of the models obtained from the BN-RNN method. In addition, it is shown that training using the proposed method requires much less CPU time and number of epochs. [ABSTRACT FROM AUTHOR]

This article presents a new macromodeling approach for nonlinear electronic components and circuits based on long short-term memory (LSTM) neural network. LSTM proposes a more efficient training process in comparison with the conventional recurrent neural network (RNN) training. Conventional structures such as RNN suffer from the gradient vanishing problem during the training process. LSTM addresses this issue and solves this problem in an efficient way. In order to train the proposed structure, some input and output waveforms of the original circuit, called training waveforms, should be obtained from simulation tools or measurements. Model creation using proposed method does not require information on details inside the components and input–output training waveforms are sufficient to construct the model. The provided numerical results in this article show that the proposed method is more efficient than RNN techniques for modeling components and packages in terms of both speed and accuracy. The findings suggest that the proposed method significantly reduces the training time in comparison with conventional state-of-art modeling techniques. Furthermore, simulation time of the obtained model from the proposed technique is less than both conventional models (such as SPICE models) used in circuit simulation tools and models obtained from conventional RNN method. Three practical examples, namely, an audio amplifier, Texas Instruments (TIs) SN74AHCT540 device, and MOS inverter, are utilized to manifest the validity of the proposed macromodeling approach. [ABSTRACT FROM AUTHOR]

In this paper, an adjoint state-space dynamic neural network method for modeling nonlinear circuits and components is presented. This method is used for modeling the transient behavior of the nonlinear electronic and photonic components. The proposed technique is an extension of the existing state-space dynamic neural network (SSDNN) technique. The new method simultaneously adds the derivative information to the training patterns of nonlinear components, allowing the training to be done with less data without sacrificing model accuracy, and, consequently, makes training faster and more efficient. In addition, this method has been formulated such that it can be suitable for the parallel computation. The use of derivative information and parallelization makes training using the proposed technique much faster than the SSDNN. In addition, the models created using the proposed method are much faster to evaluate compared with the conventional models present in traditional circuit simulation tools. The validity of the proposed technique is demonstrated through the transient modeling of the physics-based CMOS driver, commercial NXP’s 74LVC04A inverting buffer, and nonlinear photonic components. [ABSTRACT FROM PUBLISHER]

This paper presents a novel sensitivity-analysis-based adjoint neural-network (SAANN) technique to develop parametric models of microwave passive components. This technique allows robust parametric model development by learning not only the input–output behavior of the modeling problem, but also derivatives obtained from electromagnetic (EM) sensitivity analysis. A novel derivation is introduced to allow complicated high-order derivatives to be computed by a simple artificial neural-network (ANN) forward-back propagation procedure. New formulations are deduced for exact second-order sensitivity analysis of general multilayer neural-network structures with any numbers of layers and hidden neurons. Compared to our previous work on adjoint neural networks, the proposed SAANN is easier to implement into an existing ANN structure. The proposed technique allows us to obtain accurate and parametric models with less training data. Another benefit of this technique is that the trained model can accurately predict derivatives to geometrical or material parameters, regardless of whether or not these parameters are accommodated as sensitivity variables in EM simulators. Once trained, the SAANN models provide accurate and fast prediction of EM responses and derivatives used for high-level optimization with geometrical or material parameters as design variables. Three examples including parametric modeling of coupled-line filters, cavity filters, and junctions are presented to demonstrate the validity of this technique. [ABSTRACT FROM AUTHOR]

In this paper, a framework for the statistical design of the flip-flops circuits is proposed to achieve a high yield, while meeting the performance, leakage power, switching power, and layout area design specifications. The proposed design solution provides the nominal design parameters, i.e., the widths and lengths of the flip-flop transistors, which provide maximum immunity to the process variations in the transistor dimensions and threshold voltage. The proposed framework shows that for a given flip-flop design specifications, a certain yield can be achieved. To further increase this yield, the proposed framework shows which design specifications should be relaxed. The transmission gate-based master-slave flip-flop is selected as a design case study in this paper, however, the proposed framework is applicable to any other flip-flop circuit in the nanometer regime. [ABSTRACT FROM AUTHOR]