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In this paper, we consider the collaborative editing of two-dimensional (2D) data such as handwritten letters and illustrations. In contrast to 1D case, overriding of objects can have a specific meaning in editing 2D data; e.g., we can represent the relative distance of two objects and the transparency by over-riding them. This paper considers the semantics of collaborative drawing by focusing on the overriding of objects, and proposes three editing modes based on users' strokes. Proposed editing modes are realized as a part of Android application with a careful selection of the information sharing model; e.g., we can switch the shared memory model realized by Firebase Realtime Database to a distributed shared memory realized by connecting replica nodes through WebRTC, depending on the use-case.

Parallel programming models and paradigms are increasingly becoming more expressive with a steady increase in the number of cores that can be placed on a single chip. Concurrent data structures for shared memory parallel pro- grams are now being used in operating systems, middle-ware, and device drivers. In such a shared memory model, processes communicate and synchronize by applying primitive operations on memory words. To implement concurrent data structures that are linearizable and possibly lock-free or wait-free, it is often necessary to add additional information to memory words in a data structure. This additional information can range from a single bit to multiple bits that typically represent thread ids, request ids, timestamps, and other application dependent fields. Since most processors can perform compare-And-Set (CAS) or load-link/store-conditional (LL/SC) operations on only 64 bits at a time, current approaches either use some bits in a memory word to pack additional information (packing), or use the bits to store a pointer to an object that contains additional information (redirection), and the original data item. The former approach restricts the number of bits for each additional field and this reduces the range of the field, and the latter approach is wasteful in terms of space. We propose a novel and universal method called a memory word expander in this paper. It caches information for a set of memory locations that need to be augmented with additional information. It supports traditional atomic get, set, and CAS operations, and tries to maintain state for a minimum number of entries. We experimentally demonstrate that it is possible to reduce the runtime memory footprint by 20-35% for algorithms that use redirection. For algorithms that use packing, the use of the EXPANDER can make them feasible. The performance overhead is within 2-13% for 32 threads. When we compare the performance of the EXPANDER based non-blocking algorithms with the version that uses locks, we have a performance gain of at least 10-100X.

Shared Memory stands out as a sine qua non for parallel programming of many commercial and emerging multicore processors. It optimizes patterns of communication that benefit common programming styles. As parallel programming is now mainstream, those common programming styles are challenged with emerging applications that communicate often and involve large amount of data. Such applications include graph analytics and machine learning, and this paper focuses on these domains. We retain the shared memory model and introduce a set of lightweight in-hardware explicit messaging instructions in the instruction set architecture (ISA). A set of auxiliary communication models are proposed that utilize explicit messages to accelerate synchronization primitives, and efficiently move computation towards data. The results on a 256-core simulated multicore demonstrate that the proposed communication models improve performance and dynamic energy by an average of 4x and 42% respectively over traditional shared memory.

Renaming is a task in distributed computing where n processes are assigned new names from a name space of size m . The problem is called tight if m = n , and loose if m > n . In recent years renaming came to the fore again and new algorithms were developed. For tight renaming in asynchronous shared memory systems, Alistarh et al. describe a construction based on the AKS network that assigns all names within O ( log n ) steps per process. They also show that, depending on the size of the name space, loose renaming can be done considerably faster. For m = ( 1 + ϵ ) ⋅ n and constant ϵ , they achieve a step complexity of O ( log log n ) . In this paper we consider tight as well as loose renaming and introduce randomized algorithms that achieve their tasks with high probability. The model assumed is the asynchronous shared-memory model against an adaptive adversary. Our algorithm for loose renaming maps n processes to a name space of size m = ( 1 + 2 ∕ ( log n ) l ) ⋅ n = ( 1 + o ( 1 ) ) ⋅ n performing O ( l ⋅ ( log log n ) 2 ) test-and-set operations. In the case of tight renaming, we present a protocol that assigns n processes to n names with step complexity O ( log n ) , but without the overhead and impracticality of the AKS network. This algorithm utilizes modern hardware features in form of a counting device which is also described in the paper. This device may have the potential to speed up other distributed algorithms as well.

Molecular Dynamics (MD) is a computational technique with applicability in fields as diverse as material science, biomolecules and chemical physics. These applications are computationally intensive and massively parallel in nature and ideal candidate to exploit capabilities Intel Xeon Phi co-processor and Nvidia's Tesla GPU accelerators. In this work, we provide details of our experience in optimizing a molecular dynamics application on Xeon Phi. Xeon Phi is a product by Intel based on the Many Integrated Core Architecture. We exploit the 512 bit vector width of Xeon Phi through use of various techniques and achieve improved SIMD performance. We also implement shared memory model of OpenMP and reduce communication overheads between OpenMP threads by removal of reduction. These and other techniques described in the paper helped improve the applications performance on Xeon Phi by 322%.

Uintah is a software framework that provides an environment for solving large-scale science and engineering problems involving the solution of partial differential equations. Uintah uses a combination of fluid-flow solvers and particle-based methods for solids, together with adaptive meshing and synchronous task-based approach with automated load balancing. When applying Uintah to fluid-structure interaction problems, the combination of adaptive meshing and the movement of structures through space present a formidable challenge in terms of achieving scalability on large-scale parallel computers. Adopting a model that uses MPI to communicate between nodes and a shared memory model on-node is one approach to achieve scalability on large-scale systems.This scalability challenge is addressed here for Uintah, by the development of new hybrid runtime and scheduling algorithms combined with novel lock-free data structures, making it possible for Uintah to achieve excellent scalability for a challenging fluid-structure problem with mesh refinement on as many as 256K cores.

As the parallel computing technologies become mature, many computationally intensive and/or data intensive algorithms could be improved with parallelization methods. In this paper, we improve the performance of the edge extraction algorithmic program by parallelizing the sequential algorithm. We altogether propose three parallelization methods based on chip multiprocessor (CMP) clusters. The OpenMP-based method is investigated for the shared memory model and thus it is applied to single CMP node, while the three MPI-based methods are investigated for the message passing model and thus they are applied to CMP-clusters. Massive experiments verify that the parallelization methods proposed in this paper are all effective and efficient.

With the advent of the multicore era, the number of cores per computational node is increasing faster than the amount of memory. This diminishing memory to core ratio sometimes even prevents pure MPI applications to benefit from all cores available on each node. A possible solution is to add a shared memory programming model like Open MP inside the application to share variables between Open MP threads that would otherwise be duplicated for each MPI task. Going to hybrid can thus improve the overall memory consumption, but may be a tedious task on large applications. To allow this data sharing without the overhead of mixing multiple programming models, we propose an MPI extension called Hierarchical Local Storage (HLS) that allows application developers to share common variables between MPI tasks on the same node. HLS is designed as a set of directives that preserve the original parallel semantics of the code and are compatible with C, C++ and Fortran languages and the Open MP programming model. This new mechanism is implemented inside a state-of-the-art MPI 1.3 compliant runtime called MPC. Experiments show that the HLS mechanism can effectively reduce memory consumption of HPC applications. Moreover, by reducing data duplication in the shared cache of modern multicores, the HLS mechanism can also improve performances of memory intensive applications.

In recent years hardware accelerators have become a full part of the HPC domain as their peak performance has increased steadily. Although their programmability has greatly improved and different tools have been developed to smooth down their learning curve, porting legacy code to the new programming models could reveal itself a cumbersome and time-consuming process. However a large amount of code benefits from the multicore architectures using either a shared memory model or a distributed model. Our goal was to allow developers to benefit from the simplicity of OpenMP code and at the same time permitting their code to be executed on GPUs many core architectures. Thus we propose a source-to-source compiler able to automatically transform an OpenMP C code into a CUDA code, while maintaining a human readable version of the code that can be further analyzed or optimized. Using the OMPi compiler as a base ground, we implemented the "pragma omp parallel for" transformation along with data visibility clauses. The generated code is fully NVIDIA CUDA compliant and can be compiled using the nvcc compiler. In this paper we present the entire transformation process, starting from the pragma split-up and kernel generation, passing through the data visibility clauses management and ending with the device memory management and kernel launch system.

Network on Chip can be viewed as processors from various families residing on a chip. Programs issued to a particular processor type can be divided into sequential and parallel code. The processors are assumed to be connected to each other as a directed graph. The parallel code is called as a task. Each task is characterized by an estimated time for completion. This paper proposes a method to determine the allocation of the parallel tasks during program execution to the processors of the same type to achieve optimal execution time. The proposed model assumes shared memory model. A linear programming model is developed to determine the number of tasks allotted to each processor belonging to a family for any parallel code, given the average waiting time for each of the processors in the family. The proposed algorithm is simulated with an example which gives 18% improvement in performance over round robin allocation of tasks.

The wide increase of total processing cores in commodity processors tends to lighten the need for computer performance by the classical scientific problems as well as by the modern multimedia and every day embedded applications. Nevertheless, the introduction of this powerful and promising technology seems to inherit and in some cases magnify all the classical problems that already exist on the programming side of these environments. In this work we present a portable environment based on the Java platform targeting to mitigate the performance loss associated with the programming models used in modern multicore systems. We propose a shared memory model for programming modern multicore and distributed environments, presuming only minor interventions by the application programmer. We finally prove that when we use shared memory programming with a widely accepted programming language like Java, we can achieve at least comparable performance with classical though more sophisticated technologies.

A MPSOC based on Network-on-Chip (NoC) is developed and presented. Some matrix applications are developed for this platform according to the shared-memory programming model. Performance results are compared between the NoC based multiprocessor system and the traditional bus-based MPSOC. The concerns of efficient data distribution and requisition for the memory system have also been considered in this paper. A conclusion is made in the end showing the apparent advantages brought in by the NoC based MPSOC.

We investigate the relative computational power of parallel models with directed reconfigurable buses and the most powerful shared memory model, the broadcast with selective reduction (BSR). We show that these two models have the same computational power in a strong sense. We also show that the Collision write conflict resolution rule is universal on models with directed reconfigurable buses (meaning that complex conflict resolution rules such as priority or even combining can be simulated by collision with constant-time overhead). Consequences of these finding, including some real time consideration, are discussed.

The NAS Conjugate Gradient (CG) benchmark is an important scientific kernel used to evaluate machine performance and compare characteristics of different programming models. Global Arrays (GA) toolkit supports a shared memory programming paradigm and offers the programmer control over the distribution and locality that are important for optimizing performance on scalable architectures. In this paper, we describe and compare two different parallelization strategies of the CG benchmark using GA and report performance results on a shared-memory system as well as on a cluster. Performance benefits of using shared memory for irregular/sparse computations have been demonstrated before in the context of the CG benchmark using OpenMP. Similarly, the GA implementation outperforms the standard MPI implementation on shared memory system, in our case the SGI Altix. However, with GA these benefits are extended to distributed memory systems and demonstrated on a Linux cluster with Myrinet.

In this paper, we propos a new shared memory model: Transactionalmemory Coherence and Consistency (TCC).TCC providesa model in which atomic transactions are always the basicunit of parallel work, communication, memory coherence, andmemory reference consistency.TCC greatly simplifies parallelsoftware by eliminating the need for synchronization using conventionallocks and semaphores, along with their complexities.TCC hardware must combine all writes from each transaction regionin a program into a single packet and broadcast this packetto the permanent shared memory state atomically as a large block.This simplifies the coherence hardware because it reduces theneed for small, low-latency messages and completely eliminatesthe need for conventional snoopy cache coherence protocols, asmultiple speculatively written versions of a cache line may safelycoexist within the system.Meanwhile, automatic, hardware-controlledrollback of speculative transactions resolves any correctnessviolations that may occur when several processors attemptto read and write the same data simultaneously.The cost of thissimplified scheme is higher interprocessor bandwidth.To explore the costs and benefits of TCC, we study the characterisitcsof an optimal transaction-based memory system, and examinehow different design parameters could affect the performanceof real systems.Across a spectrum of applications, the TCC modelitself did not limit available parallelism.Most applications areeasily divided into transactions requiring only small write buffers,on the order of 4-8 KB.The broadcast requirements of TCCare high, but are well within the capabilities of CMPs and small-scaleSMPs with high-speed interconnects.

It is argued that the choice between the shared-memory and message-passing models depends on two factors: the relative cost of communication and computation as implemented by the hardware, and the degree of load imbalance inherent in the application. Two representative applications are used to illustrate the performance advantages of each programming model on several different shared-memory machines, including the BBN Butterfly, Sequent Symmetry, Encore Multimax and Silicon Graphics Iris multiprocessors. It is shown that applications implemented in the shared-memory model perform better on the previous generation of multiprocessors, while applications implemented in the message-passing model perform better on modern multiprocessors. It is argued that both models have performance advantages, and that the factors that influence the choice of model may not be known at compile-time. As a compromise solution, the authors propose an alternative programming model, which has the load balancing properties of the shared-memory model and the locality properties of the message-passing model, and show that this new model performs better than the other two alternatives. >

Given G=(V,E) is a simple planar graph, and it doesn't contain any odd loops, |V|=n, |E|=m. We propose an efficient parallel algorithm for edge-coloring by using /spl Delta/ colors, based on SIMD-CRCW PRAM, a kind of shared memory model that many processors can read and write a unit simultaneously. Here, /spl Delta/ is the maximum degree of vertices of G. If /spl Delta/ is an even number, the algorithm requires O(log/spl Deltaspl middot/log/sup 2/n) time and O(n/spl Delta/) processors; otherwise it requires O(log/spl Deltaspl middot/log/sup 2/n+/spl Deltasup 2/n) time and O(n/spl Delta/) processors. When /spl Delta/=O(log/sup O(1/)n), the algorithm is an efficient algorithm. >