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Short cycle test pattern can sensitize target paths deterministically and periodically in short interval. It is useful to apply the short cycle test pattern for accelerating scan-based delay measurement. This paper presents the deterministic scan-based online delay measurement using short cycle test pattern for short measurement time. Applying short cycle test pattern to scan-based online delay measurement drastically reduces the time required for iterative path sensitizations, which reduces the measurement time. It makes scan-based critical path delay measurement practical for DFS, DVS, and prediction of aging. Evaluation reveals that the cycle of the path sensitization using short cycle test pattern is 9.1 clocks on average. The average of the measurement time is 28.6 % of normal scan-based measurement. The data volume is 59.1 % of normal scan-based measurement on average. The area overhead is 19.0 % of full scan design.

Various companies must select an innovation model according to their respective strategies to realize a Hyper Smart Society (HSS). Four strategic approaches exist: resources, positioning, gaming, and learning; these respectively correspond to the linear, Klein, hypothesis-testing, and interactive innovation models. Using the Stage Gate method for the linear and Klein models, enables a concentration of the appropriate themes and management resources. In doing so, the issues to be overcome, which include selecting themes and developing human resources, can be surmounted by limiting the gatekeeper to one person or applying the Boost Gate method. Conversely, a method similar to the agile method, which involves quickly repeating a short cycle of analysis, design, implementation, and testing, is considered effective with the hypothesis-testing and interactive models.

In this paper, the quality monitoring method on the production line of engine's cylinder and block is proposed for its short cycle time and high precision. Making full use of the numerous data in MES, machine capacity exponent was calculated by calling reasonable and accurate distribution model, so as to predict the product quality and achieve the effect of advanced warning.

The myriad pathologies leading to and resulting from atrial fibrillation (AF) have led to many theories regarding how substrate should be defined and how to reconcile substrate ablation with trigger ablation. The identification of spatiotemporally stable areas of very low amplitude short cycle length CFAE in a sea of otherwise discrete normal amplitude and relatively longer cycle length electrograms led to ablate the complex fractionated atrial electrogram (CFAE) as a marker of abnormal substrate. This pure substrate-based ablation strategy has shown promising result of benefit in stroke and mortality reduction in high-risk patients. In this review which has been modified and abridged from the recent publication on this subject [1], we discuss the prevailing mechanisms underlying CFAE, how to map and ablate CFAE sites, correlation of CFAE areas to those of ganglionic plexi, clinical outcomes of the approach, and the controversy surrounding targeting CFAE as substrate sites for AF ablation.

High resolution encoders are employed to industrial equipment which is required accuracy, for example, NC machine tools, exposure systems, and so on. Generally, the velocity of machines is calculated by the difference of the position given by the encoder. Although the high resolution encoder is employed, the quantization error and the half sample delay induced by the difference cannot be avoided. These are problems in the case of required high precise velocity. In this paper, we propose an observer which can estimate state variables with reducing the quantization error. Finally, simulations and experiment with experimental precision stages are performed to show the advantages of the proposed observer.

This paper introduces interleaver constraints to eliminate low squared Euclidean distance (SED) error events for a specific serially concatenated code (SCC). These interleaver constraints eliminate specific multiple error events as well as single error events. Factor graph representations of the interleaver allows to view multiple error events as short cycles in a graph. Interleaver construction rules which eliminate short cycles for an interleaver graph representation also eliminate the minimum SED error events for this SCC.

This paper describes a redundant quartz crystal based frequency reference developed for commercial space applications. This product is an outgrowth of many years of experience providing similar functionality for military space applications, but is optimized for low cost, short cycle time commercial space applications. This device provides 3 for 1 redundancy, 8 to 24 outputs for distribution to satellite subsystems, and low power dissipation (

Recently there has been a strong story emphasis in the semiconductor industry on "time to market" and "low cost" which require short cycle time and high utilization of a minimum number of tools, respectively. There is a trade-off between cycle time and utilization. By defining utilization of tools and implementing to X-factor theory, authors developed a useful method of tool planning that meets the requirements of short product cycle time and highest output by reducing the risk of processes or tools causing bottlenecks which are applicable to all semiconductor factories.

A set of electrically tested, short cycle test chips and a methodology were developed to derive yield improvement during the transfer of 1.0 mu m and 0.8 mu m CMOS technologies from high-volume 100-mm facilities to a 150-mm fabrication facility. This resulted in a rapid drop of defect density and the correction of many systematic yield problems before full process lots were affected. The design of the test devices and the methodology is important to the success of the effort utilizing simple, statistically valid, large-scale arrays in the test chips, and a Pareto-driven, brutal focus analysis and improvement methodology. An analysis of shortcomings of using electrically tested structures only was done and possible improvements using optical defect detection equipment were identified. >

This paper describes a DSS (decision-making support system) for solving tool overlapping problems by using a real time dispatching system developed in MXIC FAB I. The problem issue and the system are first presented, followed by the description of the algorithm for solving tool overlapping. We found that operators can obtain the tool arrangement information very quickly through this DSS. With its precise forecast of coming WIP and calculation, our algorithm increases tool utilization by 10/spl sim/13% as well as delivering a short cycle time for BTO (build-to-order) products.