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P-type silicon nanowires (SiNWs) have attracted significant attention for their potential in miniaturizing sensing devices, attributed to the observed giant piezoresistive (PZR) effects. However, the application of these advantageous PZR properties of SiNWs to microelectromechanical systems (MEMS) has been hindered by unclear noise levels and complicated fabrication methods. Additionally, several previous reports of anomalous PZR effects, such as doping-type inversion in hydrogen fluoride (HF)-treated p-type SiNWs, have introduced further complexities. Consequently, addressing these unclear challenges is necessary to effectively utilize the PZR effects of SiNWs for MEMS sensing applications. In this paper, the primary causes of uncertain noises and resistance levels in HF-treated p-SiNWs and their dependence on surface effects were analyzed to optimize NW parameters. SiNWs were fabricated using a suitable MEMS fabrication method, and their noises with PZR effects were measured and compared. The results indicated that SiNWs with abnormal PZR characteristics were worse in signal-to-noise ratio (SNR) than those with bulk PZR properties attributed to the significant noise increments from the depletion effects. Based on the NW experiment and additional mechanical analyses, suitable SiNW conditions for MEMS sensing unit were optimized and selected. A miniaturized 3-axis accelerometer utilizing the optimized SiNW was developed and tested. The experimental results showed that the developed accelerometer successfully reduced the total area of the sensor structure by 35.4% when compared to commercial capacitive accelerometers while maintaining competitive performance. This result was achieved without relying on the giant or anomalous PZR effects.

The most effective way to reduce phase noise in integrated harmonic oscillators is by rising the active power in the resonator, i.e., scaling down the tank impedance and increasing power consumption. However, in widespread parallel-tank oscillators, a lower bound is readily set by the smallest inductance that can be implemented without incurring into excessive degradation of the quality factor. Emerging multicore oscillators circumvent the issue only partially. In this article, a circuit topology that breaks the phase noise barrier of parallel-tank oscillators is presented. By exploiting the same tank at the series resonance, the remarkably lower tank resistance allows to considerably rise the active power for given voltage swing. As a result, the phase noise is radically reduced without the need for aggressive scaling of the resonator inductor. Two voltage-controlled oscillators (VCOs) in a BiCMOS 55-nm technology exploiting the concept at 10-GHz center frequency are presented. The first design targets an ultra-low phase noise and, with 9% tuning range, demonstrates −138 dBc/Hz at 1-MHz offset with 1.2-V supply and an excellent −190-dBc/Hz figure of merit (FoM). The second design leverages a different implementation of the tank to expand the frequency tuning range and to trade phase noise for power consumption. The tuning range is 16% with a minimum phase noise of −133 dBc/Hz at 1 MHz and −188-dBc/Hz best FoM. To the authors’ knowledge, the presented VCOs demonstrate experimentally the lowest phase noise ever reported with fully integrated oscillators in silicon technology. [ABSTRACT FROM AUTHOR]

In the mm-wave frequency band, the rectifier’s sensitivity is the bottleneck of a wireless-powered IoT transponder’s distance. At a meter’s distance, the received power is weak, and transistors in a front end of a wireless power receiver operate in the weak inversion region. This article presents a mathematical analysis of the mm-wave multi-stage rectifier in the low-power region. A design methodology of a 57–64-GHz fully integrated eight-stage rectifier with a bulk-drain connection in 40-nm CMOS technology is presented. Parasitic effects on a multi-stage rectifier are analyzed. Based on the analysis, an intrinsic threshold voltage modulation is applied to improve the sensitivity. A tree-type power splitter is also proposed for the RF power signal’s phase balance. With this method, the RF signal arrives at each stage with an equal phase, and its suppression at the output is improved by 16 dB. This mm-wave rectifier achieves −7.1-dBm input sensitivity at 57 GHz with 1-V dc output voltage. The overall sensitivity from 57 to 64 GHz is better than −4.5 dBm. Compared to other mm-wave silicon-based rectifier state of the arts, the proposed mm-wave rectifier achieves better sensitivity while maintaining a compact size. [ABSTRACT FROM AUTHOR]

Side-channel attack (SCA) is one of the physical attacks, which will reveal the confidential information from cryptographic circuits by statistically analyzing physical manifestations. Various circuit-level countermeasures have been proposed as fundamental solutions to eliminate the correlations between side-channel information and circuit’s internal operations. The existing solutions, however, will introduce nonnegligible power and area overheads, making them difficult to be deployed in resource-constrained applications. In this article, a novel three-independent-gate silicon nanowire field effect transistor (TIGFET) with the intrinsic SCA-resilience characteristics is introduced to balance the tradeoffs among cost, performance, and security of cryptographic implementations. We construct six TIGFET-based current mode logic (CML) gates that can retain lower power variation under all possible transitions compared to the CMOS counterparts. As a proof of concept, advanced encryption standard (AES), SM4 block cipher algorithm (SM4), and lightweight cryptographic algorithm PRESENT are implemented utilizing the TIGFET-based CML gates. Correlation power attack is performed to evaluate the improvement of SCA resilience. Simulation results verify that the TIGFET-based cryptographic implementations decrease 42.37% area usage, lower 61.16% energy efficiency, reduce $5.35\times $ power variation, and achieve a similar level of SCA resistance compared to the CMOS counterpart, which is applicable for the resource-constrained applications. [ABSTRACT FROM AUTHOR]

The HfxZryO2 with high Zr content is demonstrated to form the anti-ferroelectric tetragonal phase (AFE t-phase). The peak dielectric constant (47) of Hf0.2Zr0.8O2 is achieved. By taking advantage of the high dielectric constant, the Hf0.2Zr0.8O2 is used in the gate stack on the high mobility Ge0.98Si0.02 channel to significantly enhance the drive current. Stacked two Ge0.98Si0.02 gate-all-around nanowires can have high ION per perimeter of $740~\mu \text{A}/\mu $ m at $\mathrm{V}_{\mathrm{OV}}= \mathrm{V}_{\mathrm{DS}}= 0.5\text{V}$. The thermal budget is as low as 450 °C. [ABSTRACT FROM AUTHOR]

In this work, we report the impact of source region’s random dopant fluctuations (RDFs) induced variability on n-type silicon double gate (DG)-TFETs via 3D-device simulation. We have observed that source region’s RDF induces strong variability in the analog and RF figures of merit (FOMs) of the devices. This is the first report showing detailed impact of RDF on DG-TFET device and based circuit. The impact of RDF is analyzed by taking RDF only in source region as tunneling barrier width depends mostly on source doping and so does the ON-state current. The variation of analog and RF FOMs, such as transconductance $({g}_{m})$ , transconductance generation factor $({g}_{m}/{I}_{d})$ , output resistance $({R}_{o})$ , intrinsic gain $({g}_{m}{R}_{o})$ , capacitances $({C}_{{gs}}$ , ${C}_{{gd}}$), gate delay $({T}_{m})$ , cutoff frequency $({f}_{T})$ , and subthreshold swing (SS), is reported. We benchmark the device analog and RF performance of the RDF sample with respect to continuum one. On the basis of observed effective deviation in characteristics, common-source amplifier circuit is simulated to analyze the deviation in voltage-transfer characteristic (VTC) and gain–bandwidth product (GBWP). [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a one-transistor, dynamic random access memory (1T-DRAM) with a very high retention time (RT), vertical twin gates, and a p+/i/n+ nanowire via well-calibrated TCAD simulations. The 4F2-like cell array of the proposed 1T-DRAM can be achieved by realizing twin gates vertically. This 1T-DRAM has a high read current ratio (106 at 25 °C and 1-ns read duration) of state “1” to state “0,” and, even when a severe word line (WL) and bitline (BL) disturbance is considered, exhibits a RT of ~3 s at 25 °C. The long RT, considering a severe WL/BL disturbance, increases the refresh interval time. A systematic analysis shows that the gate length can be scaled down to 10 nm with an acceptable RT (~3 s) to make the fabrication easier by lowering the height of the silicon nanowire. Based on these results, we believe that our proposed 1T-DRAM will be a strong candidate for future DRAM devices. [ABSTRACT FROM AUTHOR]

Three silicon nanowire (SiNW) field effect transistors (FETs) with 15-, 12.5- and 10.6-nm gate lengths are simulated using hierarchical multilevel quantum and semiclassical models verified against experimental ${I}_{D}$ – ${V}_{G}$ characteristics. The tight-binding (TB) formalism is employed to obtain the band structure in $\mathit {k}$ -space of ellipsoidal NWs to extract electron effective masses. The masses are transferred into quantum-corrected 3-D finite element (FE) drift-diffusion (DD) and ensemble Monte Carlo (MC) simulations, which accurately capture the quantum-mechanical confinement of the ellipsoidal NW cross sections. We demonstrate that the accurate parameterization of the bandstructure and the quantum-mechanical confinement has a profound impact on the computed ${I}_{D}$ – ${V}_{G}$ characteristics of nanoscaled devices. Finally, we devise a step-by-step technology computer-aided design (TCAD) methodology of simple parameterization for efficient DD device simulations. [ABSTRACT FROM AUTHOR]

The cross-sectional scaling-induced electronic property variations of the Ge and Si nanowires are studied numerically. After removing extra atoms from bulk materials to build the nanowires, not only the lateral quantum confinement is enhanced, but also the cross-sectional size will expand due to the breaking of the intrinsic strain balance. Compared with Si, the strain release-induced size expansion is more obvious in the Ge nanowires, shrinking the bandgaps and thus providing another bandgap modulation direction relative to the quantum confinement. At specific sizes, the strain release effect dominates the modulation and reduces the bandgaps of Ge nanowires even below the bulk value, while the reductions in Si nanowires are negligible, enlarging the band offsets of their heterostructures. As an application, the Ge/Si heterostructure tunnel FET (TFET) is designed and the TCAD simulation reveals a subthreshold swing (SS) of 13.8 mV/dec and an ON-state current of $93 ~\mu \text{A}/\mu \text{m}$ , three orders of magnitude larger than that using the bulk materials. [ABSTRACT FROM AUTHOR]

In this work, low frequency noise (LFN) in Schottky junction trigate silicon nanowire (SiNW) field-effect transistors (FETs) (SJGFETs) fabricated on bonded silicon on insulator (SOI) substrate is systematically analyzed. The LFN exhibited a typical 1/ ${f}$ spectrum and can be well described by the carrier number fluctuation (CNF) with correlated mobility fluctuation (CMF) model. It was found that CNF is the dominant component of the LFN, while CMF associated with the Coulomb scattering near the buried oxide (BOX)/SiNW channel interface plays an insignificant role. Applying a substrate bias can further modulate the LFN of the SJGFETs, and the effect is ascribed to the nonuniform energy distribution of the BOX/SiNW channel interface traps. Confining current path in the channel bulk away from the interface brought limited gain in terms of LFN performance. Finally, our experimental results suggested a possible transition of CMF mechanism from Coulomb scattering to surface roughness scattering when the current path is pushed away from the BOX/SiNW channel interface to the channel bulk. [ABSTRACT FROM AUTHOR]

Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 K. Thanks to the improved electrostatics by the scaled NW and 3D GAA structure, close to ideal transfer characteristics are obtained at both RT and 5.5 K with a sharp switching. Benefiting from less defects in Si created by the implantation into silicide (IIS) process, the band tail effects and neutral defects scattering are suppressed. Therefore, the fabricated Si GAA NW p-FETs provide very low subthreshold swing SS of 3.4 mV/dec in the weak inversion region and an average SSth of 14 mV/dec measured from the off-state to the threshold voltage, as well as an improved transconductance Gm at 5.5 K. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects are investigated in a highly-scaled gate-all-around (GAA) FET technology using Si nanowire channels with a diameter of 8 nm. n- and p-FETs are irradiated up to 300 Mrad(SiO2) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO2). At ultrahigh doses, the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H+-driven generation of interface traps at the oxide/channel interface. In contrast, FETs irradiated under negative gate bias are dominated by transconductance loss and increases of low-frequency noise, suggesting the activation of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions. [ABSTRACT FROM AUTHOR]

Heterostructure engineering in III-V vertical nanowire (VNW) MOSFETs enables tuning of transconductance and breakdown voltage. In this work, an InxGa $_{{1}-{x}}$ As channel with a Ga-composition grading (${x} \,\,=$ 1–0.4) in the channel and drain region, combined with field plate engineering, enables breakdown voltage above 2.5 V, while maintaining transconductance of about 1 mS/ $\mu \text{m}$ , in VNW MOSFETs. The field plate consists of a vertically integrated SiO2 layer and a gate contact, which screens the electric field in the drain region, extending the device operating voltage. By scaling the field plate, a transconductance of 2 mS/ $\mu \text{m}$ , alongside the breakdown voltage of 1.5 V, is obtained, demonstrating the benefit of field engineering in the drain. The scalability of the field plate and the gate is measured, showing an ON-resistance increase by 23 $\Omega \cdot \mu \text{m}$ , and transconductance decrease by 5 $\mu \text{S}/\mu \text{m}$ , per nm field plate length. This behavior is captured in a new and modified virtual source model, where device transmission and drain resistance are altered to capture the field plate scaling effect. The modeling is applied to nanowire (NW) devices with field plate lengths ranging from 5 to 115 nm, capturing accurately essential device performance parameters. Finally, a modified band-to-band (BTB) tunneling approach is used to accurately describe the device behavior above 1.5 V. [ABSTRACT FROM AUTHOR]

We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs. [ABSTRACT FROM AUTHOR]

A comprehensive computational study of gate-all-around (GAA) devices with 3-D stacked silicon nanosheets (also known as nanoribbons or nanowires) is presented in this article. Technology development guidelines are provided for low-power applications in 5-nm CMOS technology node and beyond. The 3-D stacked nanosheet devices lower the subthreshold swing, drain-induced barrier-lowering, and subthreshold leakage current by up to 20.75%, 38.89%, and 88.53%, respectively, when compared to a silicon-on-insulator (SOI) FinFET with 5-nm physical gate length and identical silicon area at ${V}_{\text {DD}} = {0.6}$ V and ${T} = {80}\,\,^{\circ }\text{C}$. The voltage gain of a minimum-sized CMOS inverter is increased by up to 157% with the 3-D stacked nanosheet devices, thereby providing robust operation with wider noise margins when compared to the SOI-FinFET technology. Furthermore, by scaling the supply voltage to 0.49 V, the energy consumption of a CMOS inverter is reduced by 53.81% with the GAA 3-D stacked nanosheet devices while providing similar output transition speed when compared to the SOI-FinFET technology. [ABSTRACT FROM AUTHOR]

In this work, we examine and benchmark the analog/RF performance metrics of silicon-based multigate devices, such as Fin-FET, gate-all-around nanowire (NW)-FET, and gate-all-around nanosheet (NS)-FET, in the ultimate scaling limit of sub-5-nm technology node. The performance analysis of multigate devices is done using a fully calibrated 3-D technology computer-aided design (TCAD) simulation based on self-consistent solutions of Poisson’s equation, drift-diffusion transport equation, and carrier continuity equation with quantum correction terms for accounting band-to-band tunneling and confinement effects. Our performance benchmarking suggests that NS-FET with (100) surface orientation is a more favorable candidate over NW-FET and Fin-FET for analog/RF applications with higher voltage gain (32 V/V), higher peak cutoff frequency (373 GHz), and higher maximum oscillation frequency (389 GHz) at the 5-nm technology node. The performance benefits of NS-FET are found to be retained by decreasing the channel length, increasing the effective device width, and stacking the multichannel. Furthermore, our studies identify the proper directions to optimizations for achieving high-frequency and high-gain RF operations with multigate devices. [ABSTRACT FROM AUTHOR]

Endurance to cyclic program/erase (P/E) in a gate-all-around (GAA)-based SONOS flash memory device is improved by Joule heat, which was driven by gate-induced drain leakage (GIDL) current (${I}_{\text {GIDL}}$) with a current level of microamperes. By use of COMSOL simulation, induced temperature (${T}$) by the ${I}_{\text {GIDL}}$ is higher at the GAA with the ONO gate dielectrics than at a GAA with a thermal gate oxide due to the confined heat inside a silicon nanowire channel wrapped by a relatively thick ONO. Furthermore, ${T}$ is high enough to cure the damage from the iterative P/E operations. For a quantitative evaluation of the damage level before and after cyclic P/E, border trap density (${N}_{\text {bt}}$) in a tunneling oxide was analyzed with the aid of low-frequency noise (LFN) measurements. The damage was almost fully cured by ${I}_{\text {GIDL}}$ without an external Joule heater or structural modifications because it is always around a MOSFET. [ABSTRACT FROM AUTHOR]

The nanowire gate-all-around structure with the ultimate channel electrostatic integrity exhibits the best immunity to short channel effects and improved scaling capability compared with other multigate structures. In this article, both the tunneling current and capacitance models are developed simultaneously for nanowire tunneling field-effect transistors (FETs). Based on the same surface potential model, the developed current model and capacitance model share the common parameters and therefore can be easily integrated as a complete model for circuit-level simulations. Moreover, there is no iterative process involved during the model derivation indicating the models would be efficient for circuit simulations. The proposed models are also implemented into a circuit simulator with SPICE net-list to simulate the inverter, NAND, and NOR gates. Correct circuit behaviors obtained validate the model compatibility with the SPICE platform and usefulness for the further investigation of nanowire-based tunnel FET (TFET) circuits. [ABSTRACT FROM AUTHOR]

The eight stacked Ge0.75Si0.25 nanosheets, the seven stacked Ge0.95Si0.05 nanowires, and the six stacked Ge0.95Si0.05 nanowires without parasitic channels are demonstrated. These highly stacked channels are made from 18 epilayers consisting of a Ge buffer, nine heavily P-doped Ge sacrificial layers, and eight GeSi channel layers with the low growth temperature (350 °C and 375 °C) to ensure the entire epilayers metastable without dislocations in the channels. The isotropic wet etching by H2O2 and NH4OH + H2O2 is used for the channel release and the removal of the parasitic channels, respectively. The delicate interplay between epilayer design and wet etching is implemented to fabricate the highly stacked GeSi channels. High inter-channel uniformity of the eight stacked Ge0.75Si0.25 nanosheets is obtained due to the superior etching selectivity. High ${I}_{\mathrm{\scriptscriptstyle ON}}$ per stack and per footprint of the seven stacked Ge0.95Si0.05 nanowires and the six stacked Ge0.95Si0.05 nanowires without parasitic channels are achieved due to the high mobility ${L}_{4}$ valleys and nanowire conduction. The reduced subthreshold slope (SS) and improved ${I}_{\mathrm{\scriptscriptstyle ON}} / {I}_{\mathrm{\scriptscriptstyle OFF}}$ are obtained by parasitic channel removal. The record ${I}_{\mathrm{\scriptscriptstyle ON}}$ of $120~\boldsymbol \mu \text{A}$ per stack ($4600~\boldsymbol \mu \text{A} / \boldsymbol \mu \text{m}$ per channel footprint) at ${V}_{\mathrm{\scriptscriptstyle OV}} = {V}_{\mathrm{\scriptscriptstyle DS}} = 0.5$ V is reached among reported Ge/GeSi 3-D nFETs. [ABSTRACT FROM AUTHOR]

The level-set method is widely used for high-accuracy 3-D topography simulations in process technology computer-aided design (TCAD) because of its robustness to topological changes introduced by the involved complicated physical phenomena. Particularly challenging are material flow processes, such as oxidation, reflow, and silicidation, as these require the solution of intricate physical models and the extension of the model-dependent velocity fields to the entire simulation domain at every time step to accurately compute the advection. This velocity extension, thus, introduces yet another computational burden at every time step, which is significant when considering that high-accuracy material flow simulations can easily require several hundred time steps and are applied multiple times in cutting-edge fabrication processes of integrated circuits. In this work, a shared-memory parallel scalar and vector velocity extension algorithm for level-set-based material flow simulations on hierarchical meshes is introduced, allowing to further reduce the turnaround time of TCAD workflows. The performance is evaluated by investigating a representative material flow simulation of 3-D thermal oxidation of silicon. A parallel speedup of 7.1 for the vector-valued extension and 6.6 for the scalar-valued extension is achieved for ten threads; the latter outperforms a previous approach by up to 60%. [ABSTRACT FROM AUTHOR]

A stabilization method is presented for the Boltzmann equation (BE) that is based on Godunov’s approach applied directly in the phase space. This makes it possible to perform transient simulations under quasiballistic conditions and to include the Pauli principle in the scattering integral without further approximations. The method ensures positive distribution functions by construction. The BE is solved self-consistently together with the Poisson and Schrödinger equations by the Newton–Raphson method for a nanowire silicon nMOSFET, for which the stationary ${I}$ – ${V}$ characteristics, the small-signal admittance parameters, and the switching behavior are calculated. The large-signal behavior of the MOSFET as an amplifier is evaluated by cyclostationary simulations including power gain and the output power at higher harmonics. The current responsivity of the MOSFET operated as a passive mixer is simulated up to terahertz (THz) frequencies including the quasiballistic case with negligible scattering. [ABSTRACT FROM AUTHOR]

Surface electrode ion trap is highly promising for practical quantum computing due to its superior controllability on the trapped ions. With advanced microfabrication techniques, silicon has been developed as an ion trap substrate for delicate surface electrodes design and monolithic electro-optical components integration. However, the high RF loss of silicon hinders the possible large-scale implementation. In this work, we demonstrate a through silicon via (TSV) integrated ion trap, which has low RF loss due to the elimination of wire bonding (WB) pads on the surface and the miniaturization of form factor. We also fabricate two types of conventional WB traps with or without a grounding screen layer. The RF performances of different ion traps are tested and compared, in terms of on-chip S-parameter, postpackaging resonance, and resulting power loss. The results show that the TSV trap has low S21 (~0.2 dB at 50 MHz), high Q factor (~22), and low power loss (0.26 W) compared to WB traps. In addition, 3-D finite element modeling (FEM) is employed for electric field visualization and RF loss analysis of different traps. The extracted results from the modeling show a decent agreement with the measurements. In addition to various RF tests, the design, fabrication, and ion trapping operation of different ion traps are presented. This work provides insights into RF loss of ion trapping devices and offers a new solution for RF loss reduction. [ABSTRACT FROM AUTHOR]

Four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-edge roughness (GER), and random discrete dopants (RDD), affecting the performance of state-of-the-art FinFET, nanosheet (NS), and nanowire (NW) FETs, are analysed via our in-house 3D finite-element drift-diffusion/Monte Carlo simulator that includes 2D Schrödinger equation quantum corrections. The MGG and LER are the sources of variability that influence device performance of the three multi-gate architectures the most. The FinFET and the NS FET are similarly affected by the MGG variations with threshold voltage and on-current standard deviations significantly lower (at least 20 %) than those of the NW FET. The LER variability has a negligible influence in the NS FET performance with $\sigma ~{V}_{T}$ values around 12 and 42 times lower than those of the FinFET and the NW FET. The three architectures are equally affected by the RDD ($\sigma {V}_{T}$ = 8 mV) and minimally influenced by the GER ($\sigma {V}_{T} \approx 4$ mV). The variability of NS FETs makes them strong candidates to replace FinFETs. [ABSTRACT FROM AUTHOR]

Semiconductor doping is limited by such practical concerns as bandgap narrowing and solid solubility limits of dopants. Bound-charge engineering (BCE) bypasses these limits by doping with surface bound charge located on the interface between a semiconductor and an adjacent low-permittivity oxide; it can be used to reduce depletion lengths of junctions in field-effect transistors (FETs). BCE is established by basic electrostatics and is widely applicable to emerging materials and novel devices. In this work, an analytical surface potential model for gate-all-around BCE-assisted silicon nanowire FETs, with arbitrary and possibly distinct spacer and gate oxides, is derived. This model is based on scaling theory and verified against atomistic quantum transport simulations; it provides an intuitive formalism for developing and modeling devices with BCE. [ABSTRACT FROM AUTHOR]

Three-independent-gate FETs (TIGFETs) are Schottky-barrier-based devices, which can be reconfigured to be either n- or p-type allowing for innovative compact logic gate implementations. In this article, we present an aggressively scaled 10-nm gate-all-around silicon–germanium nanowire TIGFET device evaluated with Synopsys Sentaurus Poisson-based Technology Computer-Aided Design (TCAD) simulations at a 0.7-V nominal supply voltage as typically used at this technology node. The operation of the TIGFET device is described in detail, with particular care given to the majority current contributions for each operating mode. When considering a silicon–germanium channel, the maximum TCAD-simulated current drive is 880.20 and $806.58~\mu \text{A}/\mu \text{m}$ for n- and p-type operation, respectively, thus making TIGFET devices competitive with FinFET technology at the 10-nm node. These simulations are verified using device physics calculations. Further simulations of the carrier densities for each of the TIGFET-operating configurations are performed to confirm that the simulated device is operating as intended. [ABSTRACT FROM AUTHOR]

We investigate the operation modes of a dual-gate reconfigurable field-effect transistor (RFET). To this end, dual-gate silicon-nanowire FETs are fabricated based on anisotropic wet etching of silicon and nickel silicidation yielding silicide-nanowire Schottky junctions at source and drain. We compare the program gate at source (PGAS) with the more usual program gate at drain (PGAD) operation mode. While in PGAD mode, ambipolar operation is suppressed, switching is deteriorated due to the injection through a Schottky barrier. Operating the RFET in PGAS mode yields a switching behavior close to a conventional MOSFET. This, however, needs to be traded off against strongly nonlinear output characteristics for small bias voltages. Our measurement results are supported by transport simulations employing a nonequilibrium Green’s function approach. [ABSTRACT FROM AUTHOR]

This article presents a highly programmable time-approximation filter (TAF) that can be embedded in a direct RF transmitter architecture. The proposed filter technique approximates the impulse response of a finite impulse response (FIR) filter with a modulated LO waveform, leading to an equivalent RF bandpass filtering during the frequency up-conversion process. The silicon prototype in 65-nm CMOS achieves an error vector magnitude (EVM) performance of −42 dB for a 20-MHz, 256-QAM signal and −43 dB for a 10-MHz, 1024-QAM signal at 2.4 GHz. Due to TAF, the out-of-band noise floor achieves −158 dBc/Hz at a 100-MHz frequency offset. [ABSTRACT FROM AUTHOR]

In this study, p-type Pi-gate (PG) poly-Si nanowire channel junctionless accumulation-mode (JAM) field-effect transistors (FETs) were successfully fabricated and their reliability was investigated. The reliability of these PG JAM FETs was found to be dependent on the effective channel doping concentration (Nch,eff). Through a negative gate bias stress (NGBS) test, we found that degradation in the average subthreshold swing (A.S.S.) and shift in the threshold voltage (VTH) increases as the Nch,eff of the PG JAM FETs decreases. Furthermore, the PG JAM FETs with a lower Nch,eff show the more severe rate of deterioration in the transconductance (Gm) and ON current (ION). By increasing Nch,eff to reduce the electric field (E-field) on the gate oxide and tune the carrier transport mechanism in the poly-Si nanowire channel, a better immunity against the NGBS test in the p-type PG JAM FETs can be achieved under a gate overdrive voltage (VGOD = VG – VTH = −3.5 V) to perform the NGBS test. [ABSTRACT FROM AUTHOR]

Over the last 11 years, the field of Memristive Sensors abruptly emerged in literature. The present review paper has the aim to acknowledge such an exciting new field of research as well as to critically review its most significant outcomes. As usual in science and technology, only the concept of a new sensor has been drawn and simulated in some cases, while real demonstrators have been designed, fabricated, and demonstrated in several other cases. Moreover, several new sensing methods have been proposed, all based on memristive conductivity. Again, the new sensing principle has been shown just once in some cases, while several different sensors have been demonstrated by applying a single consolidated method in other cases. Therefore, ultimate aim of this paper is to deeply and exhaustive review the most important steps in such a new field by entering the significant details about the several kinds of sensor, while critically commenting on the key aspects of the proposed ideas and applications. The most important milestones are outlined as appeared along the course of the last decade, by also showing the temporal perspective of this totally new recently emerged field. [ABSTRACT FROM AUTHOR]

Gate-all-around (GAA) silicon nanowire (NW) CMOS transistors demonstrate outstanding total-ionizing-dose (TID) tolerance due to the ultrascaled gate dielectric thickness, enhanced electrostatic gate control, and suppression of parasitic leakage current paths. nFETs and pFETs show similar TID responses, making the GAA NW technology an excellent candidate for CMOS IC applications in high-radiation environments. The slight degradation of the threshold voltage suggests limited charge buildup in the gate dielectrics. However, low-frequency noise and random telegraph noise measurements show the importance of change in trap configurations in both the near-interfacial SiO2 and HfO2 dielectric layers to the radiation response and reliability of GAA NW devices. These traps are most likely due to oxygen vacancies and/or hydrogen complexes. [ABSTRACT FROM AUTHOR]

Ultrafast current-driven domain wall (DW) motions have been realized in ferrimagnetic (FiM) nanowires. However, the FiM dynamics can be significantly affected by the Joule-heating. In this work, we propose a highly efficient XNOR logic gate by properly leveraging the thermal effect on the FiM DW motions. Its functionality and advantageous performance have been confirmed by the micromagnetic simulations. Moreover, majority logic and full adder functions can also be reconfigured based on the proposed scheme. Lastly, a fully FiM DW based binary neural network (BNN) is built, which provides low energy consumption, short delay and excellent accuracy. [ABSTRACT FROM AUTHOR]

Random trapping and detrapping of charged carriers in the vicinity of gate oxide/Si interface has for long been considered as the dominant noise source in Si nanowire (SiNW) FET-based biochemical sensors. Here we extend our previous work presenting a Schottky junction tri-gate SiNWFETs (SJGFET) fabricated on a bonded silicon-on-insulator (SOI) substrate, aiming for ultra-low device noise generation. The SJGFET exhibits near-ideal gate coupling efficiency with a subthreshold swing of ~66 mV/dec. Its gate-referred voltage noise, Svg, are 1.2 × 10−10 and 1.1 × 10−11 V2 μm2/Hz at 1 and 10 Hz, respectively. These Svg values are significantly lower than that of previously reported FET-based sensors. More importantly, Svg of the SJGFET are below the reported voltage noise generated by the oxide/electrolyte sensing interface. Using our SJGFET as the signal transducer can greatly relieve the concern of the adverse effect from the intrinsic device noise in biochemical sensing applications. [ABSTRACT FROM AUTHOR]

The role of indium trioxide (In2O3) decorated Si nanowires (SiNWs) based resistive sensor for selective detection of ethanol vapors at near room temperature has been successfully demonstrated. SiNWs samples were synthesized using metal assisted chemical etching technique and these were decorated by a thin film of indium followed by annealing. The sensing response was captured by measuring the change in resistance of the sensing layer using a Cr-Au inter-digitated-electrode (IDE) structure formed on top of the sensing layers. All sensors were tested for ethanol, acetone, iso-propanol (IPA), xylene, benzene and toluene vapours in the wide concentration range of 5–500 ppm and at different temperatures. Sensors based on SiNWs alone had displayed higher response towards acetone vapours whereas after heterojunction formation with In2O3, significant sensitivity to ethanol was depicted. In2O3 decorated SiNWs resulted in significant enhancement of the sensor response% towards ethanol at near room temperature. Minimum detection of ethanol at 50 ppm and 10 ppm was portrayed by SiNWs and In2O3/SiNWs based sensors respectively. It was concluded that sensing behaviour was a consequence of combinatory effect produced by the presence of both SiNWs and In2O3. A simple explanation with device schematic and band diagrams of the material are proposed to describe the sensing mechanism. This study demonstrates the significance of surface treatment of SiNWs and the role of heterostructures for tuning the sensing properties and development of wafer scalable sensors. [ABSTRACT FROM AUTHOR]

In this article, the impact of intrinsic process fluctuations on reconfigurable field-effect transistor (RFET) is investigated for the first time. Three kinds of process fluctuation sources, including line edge roughness (LER), gate edge roughness (GER), and work-function variation (WFV), are performed in RFET using MATLAB and 3-D TCAD. The variation of ON-state current ION due to LER presents a weak correlation with that of OFF-state current IOFF. Performance variation caused by GER is mainly attributed to the control GER. WFV in control gate and source dominates the variations of ON-state characteristics. The total overall performance fluctuations are primarily attributed to WFV. In the sight of ION, WFV contributed up to 84.7% and 82.8% of the total fluctuations for n- and p-type, respectively. [ABSTRACT FROM AUTHOR]

The high-frequency performance of top-gated graphene field-effect transistors (GFETs) depends to a large extent on the saturation velocity of the charge carriers, a velocity limited by inelastic scattering by surface optical phonons from the dielectrics surrounding the channel. In this work, we show that, by simply changing the graphene channel surrounding dielectric with a material having higher optical phonon energy, one could improve the transit frequency and maximum frequency of oscillation of GFETs. We fabricated GFETs on conventional SiO2/Si substrates by adding a thin Al2O3 interfacial buffer layer on top of SiO2/Si substrates, a material with about 30% higher optical phonon energy than that of SiO2, and compared performance with that of GFETs fabricated without adding the interfacial layer. From S-parameter measurements, a transit frequency and a maximum frequency of oscillation of 43 and 46 GHz, respectively, were obtained for GFETs on Al2O3 with 0.5- μm gate length. These values are approximately 30% higher than those for state-of-the-art GFETs of the same gate length on SiO2. For relating the improvement of GFET high-frequency performance to improvements in the charge carrier saturation velocity, we used standard methods to extract the charge carrier velocity from the channel transit time. A comparison between two sets of GFETs with and without the interfacial Al2O3 layer showed that the charge carrier saturation velocity had increased from 1.5·107 to 2·107 cm/s. [ABSTRACT FROM AUTHOR]

An electrical model composed of lumped elements is proposed for slow-wave microstrip lines that use grounded blind vias/nanowires to achieve the slow-wave effect. The main difference of this model, from the traditional RLGC model for transmission lines, is the modeling of the blind vias/nanowires that consider a mutual inductive coupling considered between sections of the model. Two transmission lines on two technologies are analyzed: printed circuit board (PCB) and metallic nanowire-filled membrane (MnM) substrate. The calculi for each component of the model are detailed. Electrical simulations are done, and a comparison between the measured and simulated data is shown. It is shown that the electrical model can predict the transmission lines’ behavior, especially the dispersion on the results that happen in frequency. [ABSTRACT FROM AUTHOR]

The boosted photosensing performances have been reported for Indium (In) nanoparticles (NPs) capped TiO2 nanowire (NW) array using Glancing angle deposition (GLAD) technique. The In NP based photosensor possessed high ideality factor of ~12.8 and the enhancement in photoresponsivity has been also observed. The ON/OFF switching irradiation for the In NPs based photosensor has increased from $4.6~\mu \text{A}$ to $6.2~\mu \text{A}$ and vice versa with a rise time of 0.45 sec and fall time of 0.56 sec. [ABSTRACT FROM AUTHOR]

The findings from the time-of-flight (TOF) experiment for strained silicon nanowires are reported in this article, in combination with numerical simulations demonstrating new physical features involved in the quasi-quantum regime. The drift velocity of valence holes is demonstrated to exceed greatly that of conduction electrons. These experimental data are accurately reproduced by our simulations, revealing a dramatic reduction in the hole’s effective mass as well as a significant extension of the mean-free time between two consecutive random scattering events due to combined effects of both quantum confinement and biaxial strain. Many-body theory is further introduced for calculating elastic-scattering rate of impurities with the inclusion of static screening under the random-phase approximation. Dark current, photo-current and photoluminescence spectra are all measured in our experiments, in addition to direct TOF experiment by employing a Ti-sapphire mode-locked femtosecond laser, and their data are fully analyzed and physically explained by using both simulations and many-body theory. Our observation that the Einstein’s relation does not hold true for 1-D transport under a strong electric field is supported by a quantum-statistical calculation. Our discovery with a very large hole mobility is expected to play a key role in establishing a much more straight-forward technical path towards high-performance CMOS and radio-frequency amplifiers than current ones. [ABSTRACT FROM AUTHOR]

We present the nanofabrication and transport properties of single silicon nanowires (NWs) having mean widths in the range from sub-30 to 500 nm. Hall effect measurements are undertaken in the magnetic fields of 14 T at 300 K. The NWs are defined by electron-beam lithography (EBL) using the negative tone resist hydrogen silsesquioxane (HSQ) as a mask for reactive ion etching (RIE). Silicon NWs are patterned on nonuniform highly doped n-type silicon-on-insulator (SOI) substrates. The doping profile has been observed to show a significant effect on the NW electrostatics, which in turn influences the contact and transport properties of the NWs. For the formation of Hall electrodes, we have employed an angled substrate evaporation technique, where the NW itself is used as a shadow mask and an intimate sidewall contact has been formed. The Hall electrodes are not opposite to each other in this case; therefore, the longitudinal resistance pickup had to be considered when extracting the Hall signal of the NW. The mobility of these NWs is discussed. For the narrowest 40-nm-wide silicon NW, the obtained value of mobility is 292 ± 6 cm2/Vs and, for the blanket, nonpatterned device layer, it is 100 ± 0.1 cm2/Vs. The effective mobility increases as the width of the NWs decreases. This is attributed to the reduced dimensionality of the electron transport in the NWs. Both the electrical and effective thicknesses of the NW change at small physical width, which results in enhanced electron transport within the channel and enhances the value of the measured Hall signal. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate highly scaled, non-volatile memory transistors with ferroelectric Zr-doped HfO2(HZO) as gate insulator. ${\Omega }$ -gate transistors with gate length ~30 nm and width ~85 nm were fabricated on ~20 nm thick SOI. We demonstrate robust memory operation with ≤100 ns program and erase speed at ±5 V, projected memory retention time up to 10 years at 85 °C, and ~0.5 V memory window after 108 endurance cycles. The impact of ${V} _{\text {D}}$ on erase speed provides insights into the importance of holes on memory operation. [ABSTRACT FROM AUTHOR]

The number of interface traps (${N}_{\textit {it}}$) in a gate-all-around (GAA) MOSFET that harnesses an inherent floating body, was analyzed by using the synchronized optical charge pumping (SOCP) technique. By synchronizing control timing between the MOSFET operation and optical stimulation by light, holes generated by light illumination dominantly vanished, due to surface recombination with interface traps, rather than bulk recombination in a silicon nanowire and source/drain back-diffusion. This SOCP characterized the ${N}_{\textit {it}}$ without the aid of any additional specified test structure. To demonstrate an application, the amount of interface traps originating from off-state stress was quantitatively extracted by the SOCP. [ABSTRACT FROM AUTHOR]

The self-heating effects in vacuum gate dielectric gate-all-around field effect transistors (GAA FETs) with vertically stacked 4-nm silicon nanowire (SiNW) channels are investigated by 3-D TCAD simulation. The cross-sectional dimension-dependent thermal conductivity model of the SiNW is proposed for the precise numerical simulation of self-heating effects based on the temperature-dependent thermal conductivity of the bulk silicon. The thermal conductivity model which was verified by published data indicates that thermal conductivity of 4-nm SiNW is greatly reduced to below 10 W/mK due to the pronounced phonon boundary scattering. Simulation results shows that the vacuum gate dielectric devices undergo more severe self-heating effects than the solid gate dielectric GAA SiNW FETs, resulting in more serious performance degradation. Multiple heat sources generated by the three-stacked SiNWs make heat generation and diffusion more difficult. An effective method is proposed to suppress the self-heating effects by increasing the spacing of the gas gap within in a certain range and the around ambient gas pressure. [ABSTRACT FROM AUTHOR]

In this article, an analytical thermal conductivity model for confined nanochannel in gate-all-around silicon nanowire field-effect transistors (GAA SiNW FETs) is developed by considering the limitations caused by the cross section and length. A geometry dependence of phonon mean free path (MFP) is established for quantitatively analyzing the influence of cross-sectional dimension. Furthermore, the length-induced degradation mechanism is revealed by employing the transverse transportation phonon effective MFP. The results calculated by the model which was verified by published data indicate that the thermal conductivity of confined nanochannel in the GAA SiNW FETs is suffering from a severe degradation compared to that of ultrathin silicon in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. In addition to the suppression caused by the cross-sectional boundaries, the impact of the channel length should be taken into consideration during the modeling of thermal conductivity for accurately evaluating the self-heating effects (SHEs) in GAA SiNW FETs. [ABSTRACT FROM AUTHOR]

In front of electromagnetic (EM) pollution of the environment, EM protection requires more and more efficient solutions. Multilayered films consisting of alternating stacked nickel nanowires (NWs)-based conductive layers separated by bulk polycarbonate films were fabricated as thin electromagnetic shield. The well-defined periodic arrangement of the multilayer structure with gradient NW concentration in the conductive layers demonstrates a remarkably high effective microwave absorption (reflection and transmission below $-$ 10 dB, up to 34.3 dB of absorption loss) by tuning the conductivity and magnetic permeability of each layer. The ferromagnetic nature of NWs enhances the absorption performances compared to nonmagnetic carbon nanotubes having similar conductivity. Our method provides a simple, compact, and efficient approach for the fabrication of electromagnetic interference shielding materials offering improved broadband microwave absorption. [ABSTRACT FROM AUTHOR]

This article presents a simple derivation and fast-solving scheme to extract the characteristic impedance of planar transmission lines (TLs) on lossy/dispersive substrates, by using a series resistor after one-tier multiline thru-reflect-line (TRL) calibration, for on-wafer calibration applications. The proposed method is based on the constant resistance condition of the series resistor and linear frequency response of the conductance of TL per unit length, where the parasitic inductance of the series resistor can be frequency-dependent; thus, the deviation caused by the constant inductance assumption can be observed in millimeter-wave frequencies. The proposed method is investigated using a coplanar waveguide (CPW) on a high-resistivity silicon substrate by using an integrated passive device (IPD) technology with verifications of the calibration comparison method in a frequency range of 2–110 GHz. [ABSTRACT FROM AUTHOR]

High-pressure (HP) deuterium (D2) annealing was applied to a gate-all-around (GAA) MOSFET to improve device reliability and memory performance. The structure had gate dielectrics of oxide–nitride–oxide (ONO), which completely straddled vertically stacked multiple silicon nanowires (Si-NWs) with n+ poly-Si gates. The HP D2 annealing was effective for the vertically stacked GAA MOSFET as it was for a conventional planar MOSFET. In addition, the resistance of the n+ poly-Si gate was also reduced after the HP D2 annealing. This is attributed to the passivation of defects among adjacent poly-Si grains by the HP D2. The reduced gate resistance (RG) is advantageous for decreasing RC delay. Direct characterizations of dc I – V and analyses of ac low-frequency noise (LFN) supported the abovementioned behaviors. [ABSTRACT FROM AUTHOR]

III-V vertical nanowire MOSFETs (VNW-FETs) have the potential to extend Moore’s law owing to their excellent material properties. To integrate highly scaled memory cells coupled with high performance selectors at minimal memory cell area, it is attractive to integrate low-power resistive random access memory (RRAM) cells directly on to III-V VNW-FETs. In this work, we report the experimental demonstration of successful RRAM integration with III-V VNW-FETs. The combined use of VNW-FET drain metal electrode and the RRAM bottom electrode reduces the process complexity and maintains material compatibility. The vertical nanowire geometry allows the RRAM cell area to be aggressively scaled down to $0.01~\mu ^{m2}$ enabling realization of dense memory (1T1R) cross-point arrays on silicon. [ABSTRACT FROM AUTHOR]

In this paper, we propose studying the disease spread mechanism in the atmosphere as an engineering problem. Aerosol transmission is the most significant mode among the viral transmission mechanisms that do not include physical contact, where airflows carry virus-laden droplets over long distances. Throughout this work, we study the transport of these droplets as a molecular communication problem, where one has no control over the transmission source, but a robust receiver can be designed using bio-sensors. To this end, we present a complete system model and derive an end-to-end mathematical model for the transmission channel under certain constraints and boundary conditions. We derive the system response for both continuous sources such as breathing and jet or impulsive sources such as coughing and sneezing. In addition to transmitter and channel, we assumed a receiver architecture composed of air sampler and Silicon Nanowire field-effect transistor. Then, we formulate a detection problem to maximize the likelihood decision rule and minimize the corresponding missed detection probability. Finally, we present several numerical results to observe the impact of parameters that affect the performance and justify the feasibility of the proposed setup in related applications. [ABSTRACT FROM AUTHOR]

This letter presents a flexible pressure sensor based on silicon nanowires (Si NWs) built by metal-assisted chemical (MAC) etching. The MAC etched NWs, with a height of $30~\mu \text{m}$ and a diameter as small as 200 nm, were post-treated with polydimethylsiloxane to endow the NW sensor with elasticity and high-pressure resistance. The piezoresistance of the Si NWs varies from ${1.03}\times {10}^{{6}}$ to ${5.3}\times {10}^{{4}}$ ohms as the applied pressure changes from 0 to 4.5 kPa, indicating a resistance change rate of about 94%. The Si NW sensor also exhibits a fast response and recovery time as 0.3 s, it is capable of distinguishing pressure changes as low as 0.3kPa, which is way lower than the perceivable range (10-40kPa) of human skin. [ABSTRACT FROM AUTHOR]

In this article, we propose an integrate-and-fire (IF) neuron circuit using a single-gated silicon nanowire feedback field-effect transistor that utilizes a positive feedback loop. The IF operations are investigated through mixed-mode technology computer-aided design simulations. The neuron circuit composed of four component transistors (plus one capacitor) exhibits a high firing frequency of ~20 kHz and low power and energy consumption of 7~μW and 2.9× 10−15 J. The firing frequency and spiking voltage can be controlled through external biasing voltages. Our novel neuron circuit demonstrates a promising potential for use in spiking neural network hardware for very large-scale integration. [ABSTRACT FROM AUTHOR]