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Wide-band-gap technologies enable ultra-high efficiencies in the high-frequency power conversion. However, inadequate accuracies in electrical measurements could lead to spurious efficiency measurements, even above 100%. Furthermore, bandwidth limitations, particularly of current probing, delay mismatches between current and voltage probes, loading effects, and electromagnetic interferences, make electrical techniques inappropriate for measuring extremely-low losses in switches with high dv/dt and di/dt values and magnetic components under high-frequency excitations. Calorimetric methods overcome this issue by a direct loss measurement through the generated heat. Nevertheless, limited ranges and accuracies of the existing systems hinder their application in sensitive measurements. Moreover, time-consuming calibrations with extensive data processing impede rapid design assessments. In this work, we propose a closed-type double-chamber calorimeter based on a real-time calibration between two identical chambers to eliminate extra compensation for ambient variations or changes within the system itself. By streaming the same coolant in both chambers, our system removes the need for flow measurements, enabling extremely low flow rates, which improves sensitivity and reduces complexity and system cost. The system provides an adjustable cooling and can measure losses down to 500 mW, enabling the evaluation of high-performance power converters and their components with no dependence on the geometry of the evaluated devices or systems. [ABSTRACT FROM AUTHOR]

Soft-switching power converters based on wide-band-gap (WBG) transistors offer superior efficiency and power density advantages. However, at high frequencies, loss behavior varies significantly between different WBG technologies. This includes losses related to conduction and dynamic on-state resistance (RDS(ON)) degradation, also charging/discharging of input capacitance (CISS) and output capacitance (COSS). As datasheets lack such important information, we present measurement techniques and evaluation methods for soft-switching losses in WBG transistors which enable a detailed loss-breakdown analysis. We estimate the gate loss under soft-switching conditions using a simple small-signal measurement. Next, we use Sawyer–Tower and nonlinear resonance (NR) methods to measure large-signal COSS energy losses up to 40 MHz. Finally, we investigate the dependence of dynamic RDS(ON) degradation on off-state voltage using pulsed-IV measurements. We demonstrate an insightful comparison of soft-switching losses for various normally off gallium nitride (GaN) and silicon carbide (SiC) devices. A p-GaN-gated device exhibits the most severe RDS(ON) degradation and the lowest gate loss. Cascode arrangement increases threshold voltage for GaN devices and reduces gate losses in SiC transistors; however, it leads to higher C{OSS losses. The study facilitates the evaluation of system losses and selection of efficient WBG devices based on the trade-offs between various sources of losses at high frequencies. [ABSTRACT FROM AUTHOR]

In many semiconductor technologies, including GaN, the lack of p-channel devices is a major obstacle for complementary operations. Here, we demonstrate high-performance polycrystalline diamond p-channel transistors on GaN-on-Si. Following the optimization of the microwave-plasma chemical-vapor-deposition of diamond on GaN, the polycrystalline layer was hydrogenated to form a 2D hole-gas at the surface, acting as p-channel. Relying on a rather simple fabrication process, these devices exhibited excellent electrical and thermal performances with on-off ratio of $10^{9}$ , breakdown voltage of 400 V, specific on-resistance of 84 $\text{m}\Omega \cdot $ cm2, and thermal conductivities higher than 900 W/ $\text{m}\cdot \text{K}$. The presented hetero-integration technology provides a promising platform for future complementary logic operations, gate drivers, complementary power switch applications such as integrated power inverters and converters, simultaneously serving as a very efficient thermal management solution in high power density applications. [ABSTRACT FROM AUTHOR]

We report the first demonstration of fully vertical power MOSFETs on 6.6- $\mu \text{m}$ -thick GaN, grown on a 6-inch Si substrate by metal-organic chemical vapor deposition. A robust fabrication method was developed based on a selective and local removal of the Si substrate as well as the resistive GaN buffer layers, followed by a conformal deposition of a 35- $\mu \text{m}$ -thick copper layer on the backside by electroplating, which provides excellent mechanical stability and electrical contact to the drain terminal. The fabrication process of the gate trench was optimized, improving considerably the effective mobility at the p-GaN channel and the output current of the devices. High-performance fully vertical GaN-on-Si MOSFETs are presented, with a low specific ON-resistance (${R}_{\textsf {on,sp}}$) of 5 $\text{m}\Omega $ cm2 and a high OFF-state breakdown voltage of 520 V. Our results reveal a major step toward the realization of high-performance GaN vertical power devices on cost-effective Si substrates. [ABSTRACT FROM AUTHOR]

In this letter, a light-emitting heterostructure is designed and manufactured using vertically aligned n-type zinc oxide nanorods (ZnO NRs) on n+-GaAs wafers. The chemically grown ZnO NRs were also converted to nanotubes (NTs) using 2 molar KCl solution and the device fabrication was repeated using them. Both types exhibited a significant visible light at a forward bias of 1 V but with different brightness. Photoluminescence $\sim 390$ nm from NRs and NTs was obtained and the current injection in these devices is explained by a tunneling phenomenon. [ABSTRACT FROM PUBLISHER]

Presents corrections to the above named paper. [ABSTRACT FROM AUTHOR]