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NAND flash memory is widely used in solid-state storage including SD cards and eMMC chips, in which JPEG pictures are one of the most valuable data. In this work, we study NAND flash memory-aware, long-term JPEG data protection and recovery. Our goal is to increase the robustness of JPEG files stored in flash-based storage and rescue JPEG files that are corrupted due to long-term retention. JPEG files with our proposed protection techniques are compatible with existing JPEG viewers. We conduct real-system experiments by storing JPEG files on 16 nm, 3-bit-per-cell flash chips and let the JPEG files undergo a retention process equivalent to ten years at 25 degrees Celsius. Experimental results show that the proposed techniques can rescue corrupted JPEG files to achieve a PSNR improvement of up to 23.5 dB.

Solid-state storage technology is finding increasing adoption in enterprise and data center environments due to their high reliability and reducing cost. With high performance solid-state storage devices (SSDs) internally designed as distributed resilient systems, their operational behavior under materially different workloads is described in this research. Application of interpretable machine learning on internal parametric data of SSDs enables insights on workloads' interaction with the resilient system design. After prior research demonstrated significantly different accelerated workload stress, the analysis on resilience of the SSDs under random vs. pseudo-sequential workloads emphasize the efficacy and importance of their distributed resilience schemes. As such, these results provide causational insights on the mechanism of differential stress of the workloads impacting the resilience design principles. Moreover, the results elucidate guidelines strongly relevant from design robustness perspective for research on novel SSD architectures such as the proposed Open Channel SSD, towards deployment in hyperscale and virtualization environments.

This paper addresses the problem of guaranteeing performance and predictability of NAND flash memory in a real-time storage system. Our approach implements a new flash translation layer scheme that exploits internal parallelism within solid state storage devices. We describe the Partitioned Real-Time Flash Translation Layer (PaRT-FTL), which splits a set of flash chips into separate read and write sets. This ensures reads and writes to separate chips proceed in parallel. However, PaRT-FTL is also able to rebuild the data for a read request from a flash chip that is busy servicing a write request or performing garbage collection. Consequently, reads are never blocked by writes or storage space reclamation. PaRT-FTL is compared to previous real-time approaches including scheduling, over-provisioning and partial garbage collection. We show that by isolating read and write requests using encoding techniques, PaRT-FTL provides better latency guarantees for real-time applications.

Renewable energy sources are becoming more and more widespread and practical used, but it is difficult to plan and stabilize the process of obtaining and storing this kind of energy. The hydrogen like an energy carrier is a possible decision for stable energy storage. Thanks to the hydrogen solid state storage systems based on metal hydrides is possible to store the energy, comes from renewable sources under safety and easy conditions. Historical methods of hydrogen storage like compression and liquefaction, which are established and developed now, still bring big safety problems and associated high costs of compression and cooling.

Reliability physics of the complex memory sub-system of modern, robust solid state storage devices (SSDs) under throughput acceleration stress is analyzed leveraging Machine Learning — towards understanding their inherently designed fault-tolerance schemes that mitigate expected memory degradation mechanisms through reliable life as a system. With the strength of multiple designed error-management schemes effectively countering multiple memory degradation mechanisms under stress, the developed empirical data based Machine Learning framework allows inferential and predictive assessments on reliable SSD design at system-level in a quantitative and pro-active manner. Such Machine-Learned quantitative assessments on the system-level health of individual devices can be utilized towards managing qualification reliability assessments, assessing dynamic throughput stress impact on design and/or decision-making on reliability of individual and populations of solid-state storage systems.

Solid state disk has been widely used in various storage system due to fast access speed, good shock resistance, nonvolatile and low power consumption. Generally, solid state storage media is NAND Flash. Because the blocks in a NAND flash have a limited number of erase cycles, this reduces the life of NAND flash. Wear-leveling algorithm is employed to extend the lifetime and reliability of SSDs. In this paper, we propose a novel wear-leveling algorithm based on cold, warm and hot block. First, we divide the cold block and warm block, depending on the erase count of blocks. Second, we extracted the hot data from the warm block and merge them into a new block called hot block. Third, the hot data would be stored into RAM, and warm block and cold block into NAND flash. When we update hot block, we just need to do it in the RAM. According to some experiments with correlative wear-leveling algorithms, this algorithm we propose shows the superiority of similar wear-leveling algorithm.

Recently, a new right, the “Right to be forgotten”, has been defined for privacy protection. One approach to protect personal information is to control the data's lifetime or expiration. Here, a privacy-protection solid-state storage (PP-SSS) system is proposed, in which personal data is automatically invalidated within the hardware itself. In the proposed data-lifetime management (DLM) scheme, the same physical memory cells can be programmed to have different data lifetimes.

A FPGA based storage system with NAND flash array for high speed data acquisition applications is designed and implemented. A sharing bus architecture of flash arrays and a high performance flash controller that supports the new Open NAND Flash Interface Specification (ONFI) 3.0 standard are demonstrated. The total capacity of the storage system is 1 TB and the 16 channels of flash array can achieve a high bandwidth up to 1100 MB/s. The bit error rate of the system is analyzed.

Big-data enterprise storage is escalating demand for SSD, because of SSD's high speed, low power and small form factor. As a high-speed, low power and highly reliable enterprise storage, this paper overviews the high reliability signal processing technologies and hybrid memory solution which is the best mix and match of the high capacity NAND flash memories and storage class memories with non-volatility, speed, page rewritability and high endurance.

The superior I/O performance of solid-state storage (e.g., solid-state drives) makes it become an attractive replacement for the traditional magnetic storage (e.g., harddisk drives). More and more storage systems start to integrate solid-state storage into their architecture. To understand the impacts of solid-state storage on the performance of Hadoop applications, we consider a hybrid Hadoop storage system consisting of both HDDs and SSDs, and conduct a series of experiments to evaluate the Hadoop performance under various system configurations. We find that the Hadoop performance can be increased almost linearly with the increasing fraction of SSDs in the storage system. The improvement is more significant for a larger dataset size. In addition, the performance of Hadoop applications running on SSD-dominant storage systems is insensitive to the variations of block size and buffer size, which significantly differs from HDD-dominant storage systems. By increasing the fraction of SSDs, there is no need for the Hadoop operators to consider how to carefully tune block size and buffer size to achieve the optimal performance. Our findings also indicate that the upgrade of the hadoop storage system can be achieved by increasing the capacity of SSDs linearly according to the scale of the applications.

Modern smartphones feature multiple applications which access shared data on the solid state storage within the device. As applications become more complex, contention over this memory resource is becoming an issue. This leads to increased battery drain as the applications are forced to touch the solid state device repeatedly after failing to retrieve or store data due to contention from other applications. We describe an optimistic concurrency control algorithm, combining a novel Read-Write-Validate phase sequence with virtual execution. The protocol is suitable for governing transactions operating on databases residing on resource-constrained devices. Increasing energy efficiency and reducing latency are primary goals for our algorithm. We show that this is achieved by reducing persistent store access, and satisfy real-time requirements via transaction scheduling that affords greater determinism.

Unified solid-state storage (USSS) provides high error tolerance with four techniques: reverse-mirroring (RM), error-reduction synthesis (ERS), page-RAID, and error-masking (EM). The acceptable raw bit-error rate (ABER) of NAND flash memory is enhanced by 32×, or endurance or data-retention time effectively extends by 4.2 or 34×, respectively. ABER is defined to realize BER after ECC below 10-15.

Based on the single electron tunneling and storage in an uniform nc-Si single layer within a-SiN x (or a-SiO x ) / nc-Si/a-SiN x (or a-SiO x ) structures, the nc-Si floating gate nonvolatile memories (NVM) have been fabricated. The performance of the program and erase speed as well as the retention time have been improved by using the nitrogen plasma treatments. In order to increase the storage density, the double level charge storage has been realized in the stacked nc-Si layer based MIS structures. Considering the scaling limit of charge storage in nc-Si NVM, the Si high-rich SiO x based electrically switchable resistance random access memory (RRAM) has been investigated. The mechanism of electrically switchable resistance in Pt/SiO x /Pt structure has been also discussed.

In the petascale era, the storage stack used by the extreme scale high performance computing community is fairly homogeneous across sites. On the compute edge of the stack, file system clients or IO forwarding services direct IO over an interconnect network to a relatively small set of IO nodes. These nodes forward the requests over a secondary storage network to a spindle-based parallel file system. Unfortunately, this architecture will become unviable in the exascale era. As the density growth of disks continues to outpace increases in their rotational speeds, disks are becoming increasingly cost-effective for capacity but decreasingly so for bandwidth. Fortunately, new storage media such as solid state devices are filling this gap; although not cost-effective for capacity, they are so for performance. This suggests that the storage stack at exascale will incorporate solid state storage between the compute nodes and the parallel file systems. There are three natural places into which to position this new storage layer: within the compute nodes, the IO nodes, or the parallel file system. In this paper, we argue that the IO nodes are the appropriate location for HPC workloads and show results from a prototype system that we have built accordingly. Running a pipeline of computational simulation and visualization, we show that our prototype system reduces total time to completion by up to 30%.

Object Based Storage Device (OSD) takes object as the purpose of storage and management, OSD can be regarded as the convergence of two technologies: files and blocks. The most distinct difference between OSD and traditional storage device is the storage interface, and different storage mediums also affect the performance notability. NAND flash based solid state storage has become the mainstream of next generation data storage, because it's outstanding performance. A NAND flash based OSD framework is discussed and the approaches of data rewriting and address mapping are given in this paper.

the storage for mass data in geo-information system always restricts its development. Solid State storage is an efficient storage method based on semiconductor device, with superior performance and flexible management. Aiming at meeting the storage requirement of remote sensing image and making good use of solid state storage's advantage, the paper studies storage management mode based on Flash parallel structure. According to Flash's architectures, block-organized storage method for remote sensing image is proposed and the mapping mode is shown to link block-organized data to physical address in Flash.

This paper presented a high speed data acquisition system for real-time appLication. The hardware of system mainly consists of data acquisition, distribution and storage section. A 3Gsps ultra high-speed ADC is appLied in acquisition section. In distribution section, the original data stream will be distributed into four streams. Each data stream will be stored into one soLid-state storage card which is composed of NAND flash array. In aspect of software, implementation methods of DDR3-based FIFO and NAND flash controller were introduced in detail. System evaluation results show that system achieved high bandwidth (up to 3.0GB/s) and good SNR (up to 45dB).

In order to ensure the reliability of data, ECC is increasingly used in large-capacity data Nand type Flash storage. This paper describes the ECC algorithm, and designs a special error correction method for a radar recorder. The VHDL language description of the ECC algorithm is achieved and successfully embedded into the original program recorder, needs the actual data only on clock, not requires to calculate the additional timing, and occupies less system resources when running. It can correct one bit error and detect two bit errors, become an important way in data protection, and have the significant practical application value.

Solid State Storage (SSS) will enable major advances in the evolution and revolution of computer systems and software. The inclusion of SSS technologies will expand the capabilities of these systems, allowing more complex problems to be solved faster. The use of SSS in these systems will result in increased work performed per unit time, which will generate ever increasing sets of results data, SSS will continue to drive the needs for mass storage well into the future. Moving forward, increased performance can be achieved by employing new architectures to solve latency and write capability issues that affect present system designs. Additionally, SSS can be developed to fit into many storage sockets, such as cache, due to its small size, low power, and high capacity storage. SSS will provide a catalyst to enable the multi-faceted future of Information Technology.

Over the last twenty years the interfaces for accessing persistent storage within a computer system have remained essentially unchanged. Simply put, seek, read and write have defined the fundamental operations that can be performed against storage devices. These three interfaces have endured because the devices within storage subsystems have not fundamentally changed since the invention of magnetic disks. Non-volatile (flash) memory (NVM) has recently become a viable enterprise grade storage medium. Initial implementations of NVM storage devices have chosen to export these same disk-based seek/read/write interfaces because they provide compatibility for legacy applications. We propose there is a new class of higher order storage primitives beyond simple block I/O that high performance solid state storage should support. One such primitive, atomic-write, batches multiple I/O operations into a single logical group that will be persisted as a whole or rolled back upon failure. By moving write-atomicity down the stack into the storage device, it is possible to significantly reduce the amount of work required at the application, filesystem, or operating system layers to guarantee the consistency and integrity of data. In this work we provide a proof of concept implementation of atomic-write on a modern solid state device that leverages the underlying log-based flash translation layer (FTL). We present an example of how database management systems can benefit from atomic-write by modifying the MySQL InnoDB transactional storage engine. Using this new atomic-write primitive we are able to increase system throughput by 33%, improve the 90th percentile transaction response time by 20%, and reduce the volume of data written from MySQL to the storage subsystem by as much as 43% on industry standard benchmarks, while maintaining ACID transaction semantics.

Emerging storage technologies such as flash memories, phase-change memories, and spin-transfer torque memories are poised to close the enormous performance gap between disk-based storage and main memory. We evaluate several approaches to integrating these memories into computer systems by measuring their impact on IO-intensive, database, and memory-intensive applications. We explore several options for connecting solid-state storage to the host system and find that the memories deliver large gains in sequential and random access performance, but that different system organizations lead to different performance trade-offs. The memories provide substantial application-level gains as well, but overheads in the OS, file system, and application can limit performance. As a result, fully exploiting these memories' potential will require substantial changes to application and system software. Finally, paging to fast non-volatile memories is a viable option for some applications, providing an alternative to expensive, powerhungry DRAM for supporting scientific applications with large memory footprints.

Solid state drives (SSDs) allow single-drive performance that is far greater than disks can produce. Their low latency and potential for parallel operations mean that they are able to read and write data at speeds that strain operating system I/O interfaces. Additionally, their performance characteristics expose gaps in existing benchmarking methodologies. We discuss the impact on Linux system design of a prototype PCI Express SSD that operates at least an order of magnitude faster than most drives available today. We develop benchmarking strategies and focus on several areas where current Linux systems need improvement, and suggest methods of taking full advantage of such high-performance solid state storage. We demonstrate that an SSD can perform with high throughput, high operation rates, and low latency under the most difficult conditions. This suggests that high-performance SSDs can dramatically improve parallel I/O performance for future high performance computing (HPC) systems.

In recent years, many systems have employed NAND flash memory as storage devices because of its advantages of higher performance (compared to the traditional hard disk drive), high-density, random-access, increasing capacity, and falling cost. On the other hand, the performance of NAND flash memory is limited by its “erase-before-write” requirement. Log-based structures have been used to alleviate this problem by writing updated data to the clean space. Prior log-based methods, however, cannot avoid excessive erase operations when there are frequent updates, which quickly consume free pages, especially when some data are updated repeatedly. In this paper, we propose a hybrid architecture for the NAND flash memory storage, of which the log region is implemented using phase change random access memory (PRAM). Compared to traditional log-based architectures, it has the following advantages: (1) the PRAM log region allows in-place updating so that it significantly improves the usage efficiency of log pages by eliminating out-of-date log records; (2) it greatly reduces the traffic of reading from the NAND flash memory storage since the size of logs loaded for the read operation is decreased; (3) the energy consumption of the storage system is reduced as the overhead of writing and reading log data is decreased with the PRAM log region; (4) the lifetime of NAND flash memory is increased because the number of erase operations are reduced. To facilitate the PRAM log region, we propose several management policies. The simulation results show that our proposed methods can substantially improve the performance, energy consumption, and lifetime of the NAND flash memory storage1.

While much work is being expended throughout the industry on expensive, TSV (through-silicon-via) approaches, the intent of the work reported here was to thoroughly characterize the performance and reliability of a lower cost, non-disruptive, easier to implement improvement to wire bond and TSV methods that offers broad usefulness for many applications today. Our work focused on 3D packaging for memory cards, smart phones, and solid state storage devices to minimize footprint and maximize memory capacity. By varying temperature, cure time, and order of occurrence in the process sequence, we were able to optimize the adhesion of the polymer conductors to the contacts on the die and minimize resistance. Conductor resistance of less than 0.2 ohms/mm were observed. The 3D stacks of flash memory die fabricated with this technique allowed us to reduce SSD volume by 75%, resulting in a 4X increase in memory density.

Flash memory technology has followed Moore's Law for nine generations and with the introduction of 90 nm tech-nology, moved into the nanotechnology age. Scaling is ex-pected to continue but with increasingly difficulty. In order to meet technology scaling, the mainstream transistor based flash technologies will start evolving to incorporate material and structural innovations. Based on the introduction of ma-terial innovations, it is expected that flash memory cell can scale through at least the end of the decade (2010) using techniques that are available today or projected to be available in the near future.

The MultiMediaCard is targeted at the manufacturers of small, electronic telecommunications and computing devices that are sold as mass consumer products in retail markets. The small form factor and low cost meet the miniaturization needs and low retail price requirements of the manufacturers of consumer electronic products. At the same time, the device's small footprint, low power requirements and ease of interfacing allow it to be easily incorporated into a wide variety of different products, regardless of the microprocessor utilized.