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Transistor amplification properties of a three-leg spirofluorene-based molecule are investigated, and the transistor is shown to possess usable current, voltage, and power gain. Current gain is facilitated since the source-drain legs are conjugated, whereas the gate (control) leg is unconjugated and spatially orthogonal, and voltage gain is enhanced by the efficient quantum-mechanical coupling to the gate. Full quantum-mechanical calculations were done for all three electrodes, using the density functional formalism and a plane-wave decomposition of the wave functions. [ABSTRACT FROM PUBLISHER]

It has recently been suggested that ferroelectric (FE) negative capacitance effects can be used to achieve steep subthreshold slope field-effect transistors, which are greatly desired for reducing energy consumption in modern digital electronics. Here, we propose that this concept can be improved by the introduction of a very thin metal or metal-like layer (a quantum metal) between the FE and the semiconductor channel. We show how to design this layer so that it attenuates the polarization charge of the FE, applying an appropriate charge to the semiconductor, while at the same time presenting a relatively constant capacitance to the FE layer, as is needed to stabilize the negative capacitance regime. For homogeneous polarization, we estimate that this device (a QMFeFET) can have extremely steep subthreshold characteristics (2 mV/decade over 11 decades) and that its energy and delay performance are advantageous. [ABSTRACT FROM AUTHOR]

Experimental-modeling investigation of the transient thermal crosstalk between the field-effect transistors implemented on a silicon-on-insulator substrate is reported. The measurements were performed using a high-speed electrical pulse—probe sampling technique, which allowed detection of thermally modulated subthreshold currents. The technique achieved a temperature resolution of ∼50 mK, a time resolution of 5 ns, and a temperature sensitivity of ∼0.6 μA/K. The finite-element method was used to solve the heat diffusion equation and to obtain the temperature profiles for the given device structures. The combined high-resolution experimental—simulation approach allowed the study of the thermal crosstalk between two adjacent devices and probe the local temperature at different locations of the structure. The effects of the interface quality, layer thickness, material selection, and interdevice spacing on the heat diffusion and device performance were investigated in detail. [ABSTRACT FROM AUTHOR]

This paper describes a technique for modeling single-event upsets due to ionizing radiation in a partially depleted silicon-on-insulator (SOI) MOSFET device. Two current pulses are used, one connected between the drain and body of the device, and the other connected between the body and source of the device. The physical representation of these two current sources is described in detail. Circuit modeling is verified against drift-diffusion field solver modeling and hardware experiments. The effects of manufacturing variation and operating condition variation on the qCrit of circuit storage elements are explored. [ABSTRACT FROM AUTHOR]

Various nonplanar, multigate field-effect transistors (FET) structures have been reported that offer better gate con- trol than planar MOSFETs. In the nanometer regime, however, multigate (nanowire) structures also suffer strong quantum con- finement, which causes deleterious effects such as large threshold voltage variation. In this paper, we propose a general approach to compare planar versus nonplanar FETs with the consideration of both electrostatic integrity (gate control) and quantum confinement (the so-called "EQ approach"). With this EQ approach, we show that the cylindrical wire FET and the planar double-gate MOSFET have approximately equal scaling capability for a (001)-oriented wafer, while the nonplanar wire structures are significantly better for other wafer orientations [e.g., (011)] where the effective mass in the confinement direction of the planar MOSFET is relatively small. [ABSTRACT FROM AUTHOR]

The electrical characteristics of a heterojunction tunneling field-effect transistor (HETT), with a p-type \Si0.75\Ge0.25 source, have been measured as a function of strain. HETTs with channel transport and applied strain both in the [110] direction show a smooth monotonic change in drain current over a range of 0.09% compressive to 0.13% tensile strain. A measure \gamma = (d/d\ln JD)(d\ln JD/ds)\verts = 0 of the effect of strain s on tunneling current JD is proposed, which captures the dependence of the tunneling exponential argument on strain. An experimental value of \gamma = - \11.7 is extracted for the tensile case and compared to simulation results. We found theoretically that the value and sign of \gamma depend sensitively on the built-in strain at the Si–SiGe interface. [ABSTRACT FROM AUTHOR]

A distributed contact model is presented for a 1-D quasi-ballistic conductor deriving a contact resistance versus contact length as a hyperbolic cotangent relationship in terms of the quantum of resistance, the coupling conductance gc of the contact, and the ballistic mean free path (\lambdab). The model gave excellent fits to recent contact resistance-versus-contact length data for carbon nanotubes giving gc = \2 \ \mu\S/nm and \lambdab = \380 \ \nm. [ABSTRACT FROM PUBLISHER]

A simple potential mapping is used to show that tunneling through a single barrier, as in Schottky-barrier tunneling or source-to-drain tunneling in MOSFETs, cannot give rise to subthreshold swings below the thermionic limit (60 mV/decade at room temperature). While cognizant of the difficulty of proving a negative, it is thus highly unlikely that Schottky-barrier tunneling alone can result in reported instances of subthreshold swings that are less than 60 mV/decade. [ABSTRACT FROM AUTHOR]