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Spin logic devices based on domain wall (DW) motion offer flexible architectures to store and carry logic information in a circuit. In this device concept, information is encoded in the magnetic state of a magnetic track shared by multiple magnetic tunnel junctions (MTJs) and is processed by DW motion. Here, we demonstrate that all-electrical control of such nanoscale DW-based logic devices can be realized using a novel MTJ stack. In addition to field-driven motion, which is isotropic, we show the directional motion of DWs driven by current, a key requirement for logic operation. Full electrical control of an AND logic gate using DW motion is demonstrated. Our devices are fabricated in imec’s 300-mm CMOS fab on full wafers, which clears the path for large-scale integration. This proof of concept, thus, offers potential solutions for high-performance and low-power DW-based devices for logic and neuromorphic applications. [ABSTRACT FROM AUTHOR]

Low write error rate (WER) is an important requirement for spin-transfer torque magnetic random access memory to be developed as a product. However, there have been reports about back-hopping phenomena that disturb achieving low WER. We demonstrate the experimental observation of back-hopping from the behavior of the WER in perpendicular magnetic tunnel junctions. WER decreases as pulse voltage (Vp) increases, but increases back as Vp increases further. It is attributed to the back-hopping, which originates from flipping of the reference layer (RL) and consequent alternating reversal of RL and free layer. Thus, it is necessary for the RL to be more stable and robust to avoid the back-hopping and to achieve low WER. We performed switching experiments on the devices of different stacks, which reveal back-hopping was the most severe in a magnetic tunnel junction device with the weakest coupling strength of the RL, and was significantly suppressed with a strongly coupled RL. [ABSTRACT FROM PUBLISHER]

Spin-transfer torque magnetic random access memory (STT-MRAM) is currently explored to challenge the dynamic random access memory and embedded memory applications. Perpendicular magnetic tunnel junction (p-MTJ) stacks used in the STT-MRAM must be compatible with CMOS back-end-of-line processing, such as high perpendicular magnetic anisotropy, high tunnel magnetoresistance (TMR), and intact resistance area (RA) product at temperatures, as high as 400 °C. In this paper, we deposited a bottom-pinned Co/Ni-based p-MTJ stack with a trilayered Co/spacer/CoFeB as a reference layer and a CoFeB film as the storage layer. By replacing the standard Ta spacer material with CoFeBTa, the thickness of the spacer layer can be increased from 4 to 8 Å without TMR and RA penalty, which is beneficial to process controllability. Moreover, the TMR increases for an 8 Å CoFeB polarizer from 125% to 145% for a similar RA product after a 300 °C 30 min anneal. In addition, the thermal budget of the p-MTJ stack containing a CoFeBTa spacer was improved. The p-MTJ stack with a 12 Å CoFeBTa reference layer spacer can even withstand annealing at 400 °C for 90 min and can retain a TMR value of 100% at RA 10 \Omega \cdot \mu \textm^2 , while TMR dropped below 40% for the p-MTJ stack containing a pure Ta spacer layer. [ABSTRACT FROM PUBLISHER]

Presents a simplified derivation of the k-space method for ultrasonic pulse propagation in inhomogenous tissue. Summary of the k-space algorithm; Temporal and spatial sampling criteria; Effects of discontinuities.