179 results on '"Svensson, C."'
Search Results
2. A 3.4 GB/S Low Latency 1 Bit Input Digital FIR-Filter in 0.13 ¿M CMOS
3. High Power LDMOS Transistor for RF-Amplifiers
4. Designing of High Efficiency Power Amplifier Based on Physical Model of SiC MESFET in TCAD
5. An on-chip delay- and skew-insensitive multicycle communication scheme
6. A 3Gb/s/wire global on-chip bus with near velocity-of-light latency
7. Capacitive crosstalk effects on on-chip interconnect latencies and data-rates
8. A 750 MHz to 3 GHz tunable narrowband low-noise amplifier
9. A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTE.
10. Envelope detector sensitivity and blocking characteristics.
11. Power consumption bounds for SAR ADCs.
12. A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS.
13. A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS.
14. Low-power, high-speed, and low-noise X-ray readout channel in 0.18µm CMOS.
15. A 0.5–6GHz low gain linear RF front-end in 90nm CMOS.
16. 2.6 Gb/s over a four-drop bus using an adaptive 12-tap DFE.
17. Highly linear wideband low power current mode LNA.
18. 3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus.
19. Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS.
20. A 3.4 GB/S Low Latency 1 Bit Input Digital FIR-Filter in 0.13 μM CMOS.
21. A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS.
22. An RF Sampling Radio Frontend Based on ΣΔ-Conversion.
23. On the power consumption of analog to digital converters.
24. Blind Adaptive Mixed-Signal DFE for Gb/s, Multi-Drop, Buses.
25. Noise Analysis And Noise Estimation Of An RF Sampling Front-end Using An SC Decimation Filter.
26. Bulk Wafer Defects Observable in Vision Chips
27. Synchronous latency-insensitive design for multiple clock domain.
28. Timing closure through a globally synchronous, timing partitioned design methodology.
29. High-speed on-chip interconnect modeling for circuit simulation.
30. Channel length as a design parameter for low noise wideband LNAs in deep submicron CMOS technologies.
31. Bitline leakage equalization for sub-100nm caches.
32. Full-custom vs. standard-cell design flow - an adder case study.
33. A tuned, inductorless, recursive filter LNA in CMOS.
34. Low-power, low-latency global interconnect.
35. Optimum voltage swing on on-chip and off-chip interconnects.
36. Low power mixed analog-digital signal processing.
37. 10-100 Gb/s throughput CMOS techniques.
38. Configuration-based architecture for high speed and general-purpose protocol processing.
39. Circuit technique for accurate soft error rate measurements.
40. High speed electronics interfacing fiber networks.
41. Self-tested self-synchronization by a two-phase input port.
42. Self-synchronized vector transfer for high speed parallel systems.
43. System level policies for fault tolerance issues in the FERMI project.
44. Hydrogen sensitive MOS structures.
45. A VLSI architecture for an 80 Gb/s ATM switch core.
46. Supervision of Flooded and Valve Regulated Sealed Lead-Acid Batteries.
47. Near-sensor image processing, a VLSI realization.
48. A digital clock generator for an ATM switch implemented with multiphase clock.
49. 16-Gbit/s measurements on a 0.8-µm CMOS sub-sampling circuit.
50. A 1-MHz and 16-bit /spl Sigma//spl Delta/ DAC with a 224th-order reconstruction FIR-filter using only 9 nonzero taps.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.