Search

This paper describes a new method to design a static concentrator which is wide acceptance angle. The structures are the lightguide and a micro prism arrays to collect the sunlight from different incident angles. This innovative concentrator is 31% efficiency on normal incidence and 15° acceptance angle.

A cylinder-type Metal-Insulator-Metal (MIM) capacitor integrated with advanced 28nm logic High-K/Metal-Gate (HKMG) process for embedded DRAM has been developed. The stacked cell capacitor is formed using low temperature high-K dielectrics to achieve sufficient storage capacitance without significantly impacting logic transistors. This paper describes techniques to achieve cylinder-type MIM capacitor's capacitance >10fF/cell and keep the low leakage (10 years). The test vehicle is composed of 72 macros of 4.5Mb each. We successfully demonstrate fully functional good yield of 28nm eDRAM 324Mb test vehicle with access speed >330MHz.

A highly manufacturable embedded DRAM technology at 40nm node is presented. This report provides the characterization data of 128Mbit embedded DRAM test vehicle fabricated by 40nm eDRAM 200MHz low power process. The test vehicle is composed of 32 macros and each macro unit is 4Mb with configuration 32k×128 bits. The process is cost effective and compatible to our low power Logic core process with three additional critical masks to the base process. The DRAM memory cell consists of a high performance pass gate transistor and a metal-insulator-metal (MIM) storage capacitor with a cell size of 0.0583 um2 (< 1/4 of SRAM 0.242 um2) and small macro size of 0.145 mm2 per Mega bits (Mb). The stacked cell capacitor is formed using low temperature processed high-k dielectrics to achieve sufficient storage capacitance in DRAM cell. Low cell device leakage below 20 fA/cell at 105°C with silicided node process coupled with the high-k storage capacitance. The macro design for random access speed can operate from 25MHz to 200 MHz comparable to 6T SRAM. It has built-in ECC parity generation and correction circuits with memory storage space used for storing parity bits. The characterization is based on 200MHz, covering Vcc+/−15% at 125°C/ 105°C/ 25°C/ −40°C. Process corner skew includes core device corners TT/FS/SF/FF/SS and fast/slow cell device. Highly manufacturing yield of 128Mb macro is achieved to demonstrate the maturity of technology. The excellent cosmic ray (neutron) soft error rate (SER) performance of less than 4FITs/Mb is also achieved. The integration technologies can be applicable to the future embedded DRAM in 28nm, 20nm node and beyond.

Dielectric droplets are successfully manipulated by electropolarization forces in a parallel plate device, which extends the liquid handling capability of digital microfluidics from merely conductive droplets to dielectric ones. Actuations of silicone oil, decane, and hexadecane droplets in a 150-mum-high gap between parallel plates are demonstrated. Silicone oil droplets of different viscosities, 20 and 50 cSt, are transported and split in various gaps heights, demonstrating the manipulation capabilities of electropolarization forces. The threshold and splitting voltages are measured and compared. Moreover, the relationship between the velocity and driving voltage is studied.