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We present an electroabsorption modulated laser based on an identical epitaxial scheme, side-wall grating, on- chip microwave probe interface, and a new low-permittivity planarization method. The modulation speed is significantly increased by reducing the electrode capacitance by planarizing with a 5- $\mu \text{m}$ -thick HSQ layer. Furthermore, implementing the electrode with a direct ground-signal-ground probe interface provides a straightforward interconnection that obviates the need for an external circuit and bonding wires. The device operates at 1565 nm wavelength with stable single-mode lasing, no mode-hopping, and a side mode suppression ratio above 35 dB. An extinction ratio of 19.5 dB was recorded at the maximum modulator bias of −4 V. The electrical to optical power response of the modulated signal at–3-dBo demonstrated a 19 GHz bandwidth at an extinction ratio of 7 dB, which supports error-free data transmission up to 27 Gbit/s. [ABSTRACT FROM AUTHOR]

A two-coil magnetic core inductor that works under a low-frequency alternating current is proposed to increase the detection area of SECT (Stepped Eddy Current Thermography). As the amplitude of the alternating current is small, the heating problem of the coil is ignored. And the cooling equipment is reduced that decreases the cost of the detection system. Additionally, the split structure inductor is studied, which confirms this structure is suitable for SECT and provides a reference for the design of an adjustable exciting inductor. The detection system for detecting subsurface defects is established in numerical models and experiments. The results indicate this detection system is suitable for detecting large-sized subsurface defects in a large area. Conclusions of the amplitude contrast in the heating process and the phase contrast in the cooling process suitable for defect depth analysis are obtained through the post-processing of thermal data. [ABSTRACT FROM AUTHOR]

The usage of too many sizeable capacitors significantly increases the volume and cost of the modular multilevel converter (MMC), and limits its spread in medium- and high-voltage applications. By adding a buck-type active power filter (APF) circuit into a particular MMC topology [of which each phase multiplexes one submodule (SM)], a modified MMC (APF-M3C) topology, which inherently has the ability to suppress capacitor voltage fluctuations and decrease the power losses compared with conventional MMC topology, is proposed in this article. Both the SM capacitor voltage ripples, which can be reduced up to 50% of original value and are related to the SM capacitance, and the arm currents, which are related to SM power losses, are calculated in detail. Its topology, and operating principle is presented in detail, and a novel modulation method for the APF-M3C topology are proposed. In addition, an improved control method for the voltage balancing is also recommended to further reduce system cost and power losses. Finally, the APF-M3C topology and traditional MMC simulation and experimental platforms were built. Simulations and experimental results verify the feasibility and effectiveness of the APF-M3C topology and control strategy by comparing with the conventional MMC. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC) topology has been widely used in the medium-/high-voltage applications. However, large capacitance is needed to suppress submodule (SM) capacitor voltage ripples. This article presents a modified MMC with the active power filter (APF-MMC) paralleled between the Nth SM of the upper arm and the first SM of the lower arm in each phase without changing the original topology. It is intended to decrease the capacitor voltage fluctuations and power losses of SMs by diverting the phase low-frequency ripple powers into the storage capacitor of the additional active power filter circuit. Both the detailed SM capacitor voltage fluctuations, which can be reduced up to 50% of the original value in the traditional MMC topology, and the SM average currents, which are proportional to SM switching losses and can be reduced up to 87.83% of the original value, are analyzed. The arm rms currents are also derived, which are related to SM conduction losses. Moreover, the operating principle, modulation method, and control strategy are presented in detail. Finally, the APF-MMC and the traditional MMC topology simulation and experimental platforms were built. The simulation and experimental results demonstrate the validity and performance of the APF-MMC topology and control strategy by comparing with the traditional MMC topology. [ABSTRACT FROM AUTHOR]

This paper presents a novel Fourier-domain optical coherence tomography (FDOCT) imaging processor capable of performing all image formation operations, including dc removal, resampling, real-valued fast Fourier transform (RFFT), and display rendering. Optimizing an RFFT unit through complex-valued FFT computation makes it possible to reduce the clock rate required for the RFFT and post-RFFT units by half, thereby enhancing energy efficiency. A novel resource-sharing scheme further enables calibration (i.e., calculation of resampling indices) awareness checking with minimal area overhead. This makes the proposed FDOCT imaging processor ideally suited to portable OCT application. A test chip operating at dual 80/40 MHz was designed using the Taiwan Semiconductor Manufacturing Company 0.18- $\mu \text{m}$ technology. In postlayout simulation of FDOCT imaging mode, the test chip was shown to consume only 283.6 mW, which represents a power saving of 29% compared to an equivalent design without optimization. The proposed design was also verified at the system level using a field programmable gate arrays (FPGA) platform. In evaluation experiments, we could achieve 78-KHz A-line scan and 30-fps $512\times 1000$ OCT image display. The developed FPGA design also supports calibration awareness check using modest hardware resources. [ABSTRACT FROM AUTHOR]