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In light of the rapid advancements in big data and artificial intelligence applications, heterogeneous computing (HGC) platforms that integrate diverse computing units have gained traction with the aim of achieving energy efficiency and high performance. A custom topology-based optical network-on-chip (ONoC) that provides unparalleled diversity between computing nodes is expected to be the next-generation communication infrastructure for meeting the bandwidth and energy efficiency requirements of HGC. One of the recent challenges in the field of ONoCs is to accelerate multicast routing via wavelength division multiplexing (WDM), which dispatches data parallelly across non-interfering wavelengths. The optimization of network throughput and laser power efficiency revolves around two factors: the number of wavelengths and optical signal-to-noise ratio (OSNR). Accordingly, we introduce OSNR-aware wavelength allocation and branching methods for multicast routing (OWBM) tailored to an HGC platform in a customized ONoC. OWBM increases the wavelength resource efficiency by establishing independent routing paths in the partitioned destination nodes such that each routing path is guaranteed to be prevented from overlapping among the partitions. Moreover, the adaptive branching mechanism of OWBM adaptively selects path-based routing and OSNR-aware routing on the fly according to the wavelength allocation cases, further augmenting the throughput and laser power efficiency. Consequently, OWBM outperformed conventional tree- and path-based multicast approaches by elevating the average throughput by 47.39% and curbing the laser power consumption by up to 35.92% in various convolutional neural network benchmarks. Compared with the existing ONoC wavelength allocation techniques, the OWBM demonstrated a maximum of 42.46% enhanced wavelength utilization on a 64-core HGC platform.

Belady’s algorithm is widely known as an optimal cache replacement policy. It has been the foundation of numerous recent studies on cache replacement policies, and most studies assume this as an upper limit. Despite its widespread adoption, we discovered opportunities to unleash the headroom by addressing cache access types and implementing cache bypass. In this study, we propose Stormbird, a cache replacement policy that synergistically integrates the extensions of Belady’s algorithm and the power of reinforcement learning. Reinforcement learning is well-suited for cache replacement policy problems owing to its ability to interact dynamically with the environment, adapt to changing access patterns, and optimize the maximum cumulative rewards. Stormbird utilizes several selected features from the reinforcement learning model to enhance the instructions per cycle efficiency while maintaining a low hardware area overhead. Furthermore, it considers cache access types and integrates dynamic set dueling techniques to improve the cache performance. For 2 MB last-level cache per core, Stormbird achieves an average instructions per cycle improvement of 0.13% over the previous state-of-the-art on a single-core system and 0.02% on a four-core system while simultaneously reducing hardware overhead by 62.5%. Stormbird incurs a low hardware overhead of only 10.5 KB for 2 MB last-level cache and can be implemented without using program counter values.

One of the vital challenges for the binary neural networks (BNNs) is improving their inference performance by expanding their data representation capabilities for figuring out delicate patterns and nuances in the data. Addressing the explosive computational demands on neural network training is essential to guarantee sustainable development and scalable deployment. However, mitigating the increase in the computational cost during the training phase is critical for ensuring sustainability and scalability during deployment. In this study, an advanced sign-flipping-aware optimizer (SFAO) that focuses on BNNs was introduced to diminish the computational burden. SFAO balanced the model performance and computational cost through sign-flipping-aware updating rules throughout the training of BNNs. SFAO optimizer, tailored for BNNs with binary weight-specific updating rules, considerably reduced the computing resources needed for training on the CIFAR-10 dataset. Specifically, it surpassed the conventional full-precision updating rule by reducing the total instruction count by 21.89%. In contrast, SFAO showed a marginal 0.44% decline in the image classification accuracy relative to the updating rules for the full-precision parameters. Furthermore, the implementation of early stopping using the sign flip rate led to a notable reduction of 9.37% in the average computation time per network for the ImageNet dataset.

As the applications for artificial intelligence are growing rapidly, numerous network compression algorithms have been developed to restrict computing resources such as smartphones, edge, and IoT devices. Knowledge distillation (KD) leverages soft labels derived from a teacher model to a less parameterized model achieving high accuracy with reduced computational burden. Moreover, online KD provides parallel computing through collaborative learning between teacher and student networks, thus enhancing the training speed. A binarized neural network (BNN) offers an intriguing opportunity to facilitate aggressive compression at the expense of drastically degraded accuracy. In this study, two performance improvements are proposed for online KD when a BNN is applied as a student network: 1) parameterized weight clipping (PWC) to reduce dead weights in the student network and 2) quantization gap-aware adaptive temperature scheduling between the teacher and student networks. In contrast to constant weight clipping (CWC), PWC demonstrates a 3.78% top-1 test accuracy enhancement with trainable weight clipping by decreasing the gradient mismatch with CIFAR-10 dataset. Furthermore, the quantization gap-aware temperature scheduling increases the top-1 test accuracy by 0.08% over online KD at a constant temperature. By aggregating both methodologies, the top-1 test accuracy for CIFAR-10 dataset was 94.60%, and that for Tiny-ImageNet dataset was comparable to that of the 32-bit full-precision neural network.

The processing of data-intensive applications, followed by an unprecedented amount of data traffic, drives explosive accesses to the memory subsystem. The overloaded memory subsystem experiences increased data access latency. To expedite data access, a network caching technique that leverages network-on-chip (NoC) virtual channels (VCs) as an expanded memory subsystem has emerged. Previous network caching studies focused on utilizing VCs on the NoC’s local input port as a victim cache to reduce local data access latency. In contrast to previous studies, we explore the opportunity of mitigating problems associated with shared data access via in-network caching for directory entries (NCDE), which can utilize every input port’s VCs to hold directory entries. NCDE exploits VCs as the victim and prefetch buffers of the directory entries, each reducing directory eviction-induced invalidations and simplifying the cache-to-cache (C2C) data transfer. The effectiveness of NCDE was evaluated using a gem5 full-system simulator, and the results show that the average memory access time (AMAT) and workload execution time were reduced by 7.69% and 5.82%, respectively. As a cost for accelerating the data access latency, implementing NCDE incurs a negligible router area overhead of 1.56%.

Many deep learning frameworks utilize GEneral Matrix Multiplication (GEMM)-based convolution to accelerate CNN execution. GEMM-based convolution provides faster convolution yet requires a data conversion process called lowering (i.e., im2col), which incurs significant memory overhead and diminishes performance. This paper proposes a novel hardware mechanism, called On-the-fly Lowering Engine (OLE), to eliminate the lowering overheads. Our goal is to offload the lowering overheads from the GEMM-based convolution. With OLE, the lowered matrix is neither pre-calculated nor stored in the main memory. Instead, a hardware engine generates lowered matrix on-the-fly from the original input matrix to reduce memory footprint and bandwidth requirements. Furthermore, the hardware offloading eliminates CPU cycles for lowering operation and overlaps computation with lowering to hide the performance overhead. Our evaluation shows that OLE can reduce memory footprint of convolutional layer inputs down to $\frac {1}{12.5}\times $ and the overall memory footprint by up to 33.5%. Moreover, OLE can reduce the execution time of convolutional layers by 57.7% on average, resulting in an average speedup of $2.3\times $ for representative CNN models.

Processing-in-memory (PIM) comprises computational logic in the memory domain. It is the most promising solution to alleviate the memory bandwidth problem in deep neural network (DNN) processing. The hybrid memory cube (HMC), a 3D stacked memory structure, can efficiently implement the PIM architecture by maximizing the existing legacy hardware. To accelerate DNN inference, multiple HMCs can be connected, and data-independent tasks can be assigned to processing elements (PEs) within each HMC. However, owing to the packet-switched network structure, inter-HMC interconnects exhibit variable and unpredictable latencies depending on the data transmission path and link contention. A well-designed task schedule using context switching can effectively hide communication latency and improve PE utilization. Nevertheless, as the number of HMC increases, the variability of a wide range of inter-HMC communication latencies causes frequent context switching, degrading overall performance. This paper proposes a DNN task scheduling that can effectively utilize task parallelism by reducing the communication latency variance owing to HMC interconnect characteristics. Task partitions are generated to exploit parallelism while providing inter-HMC traffic within the sustainable link bandwidth. Task-to-HMC mapping is performed to hide the average communication latency of intermediate DNN processing results. A task schedule is generated using retiming to accelerate DNN inference while maximizing resource utilization. The effectiveness of the proposed method was verified through simulations using various realistic DNN applications performed on a ZSim x86-64 simulator. The simulations revealed that DNN processing with the proposed scheduling improved the DNN processing speed by reducing the processing time by 18.19% over conventional methods where each HMC operated independently.

The explosive growth of deep learning (DL)–based artificial intelligence (AI) applications necessitates extraordinary computing capabilities that cannot be achieved using traditional CPU standalone computing. Therefore, the heavy mission-critical DL kernel computing currently relies on a heterogeneous computing (HGC) platform integrated with CPUs, GPUs, and accelerators, as well as substantial data storage elements. However, the metallic electrical interconnection in the existing manycore platform would not be sustainable for handling the massively increasing bandwidth demand of big data driven AI applications. Incorporating an optical network-on-chip (ONoC) for providing ultrahigh bandwidth, we propose a rapid topology generation and core mapping of ONoC (REGO) for energy-efficient HGC multicore architecture. The genetic algorithm (GA)-based REGO utilizes the structural characteristics of the optical router to the fitness function and thus compromises the trade-off between the required throughput, optical signal-to-noise ratio (OSNR), and total energy consumption. Furthermore, the crossover step accelerates the convergence speed by suppressing randomness in the GA, thus significantly reducing excessive running time owing to the NP-hard property. The generated ONoC through REGO demonstrates, on an average, an increase of 63.29 % and 22.80 % in throughput and a decrease of 50.24 % and 9.56 % in energy per bit, in the VGG-16 and VGG-19 compared with the conventional mesh- and torus-topology-based ONoCs, respectively.

Network-on-chip (NoC) has become the mainstream fabric architecture for chip multiprocessor (CMP) design. Owing to the market-driven advancement of modern applications in CMP, multicast traffic is aggressively increasing to support barrier synchronization, multithreading, and cache coherence protocols. Although multicast by branching of packets in the NoC router facilitates shortest path routing, additional branching-induced deadlocks must be circumvented. Existing NoC studies on deadlock-free minimal path routing in multicast traffic have typically deployed additional virtual channels or large buffers to hold entire packets, thereby significantly increasing the router area. Focusing on the area-efficient solution while sustaining the performance, we propose a novel multicast router using buffer sharing (MRBS) to guarantee deadlock-free multicast routing by exploiting the spatial diversity of the input buffer. MRBS ensures minimal path routing without requiring additional virtual channels or large buffers to hold entire packets. Extensive experiments were conducted by varying the buffer, packet, and network sizes, as well as the number of destinations per packet, under random multicast traffic with diverse injection rates. Simulation results show that MRBS achieves a 39.3 % improvement in the area-delay product on average for various network sizes compared to the conventional tree-based router.

The advances in silicon photonics technology have facilitated the realization of optical network-on-chips (ONoCs) to cope with the physical limitations of metal interconnections in traditional CMOS integrated circuits. As the performance and reliability of optical links are adversely affected by insertion losses and crosstalk, which inevitably occur during the propagation of optical signals, optimizing the power of a laser source requires a sophisticated analysis of the optical signal-to-noise ratio (OSNR). Calculating the worst-case OSNR for all possible communication links in an ONoC is an NP-hard problem even under the assumption of a single-wavelength laser source. Moreover, when expanding the design space by accommodating wavelength-division multiplexing (WDM), semiconductor optical amplifier (SOA), diverse topologies, and the associated router architectures, the computational complexity becomes excessive. Therefore, in this study, we propose an extended worst-case OSNR search algorithm (EWOSA) that significantly reduces the computational burden through a preprocessing algorithm that reduces the number of candidate paths when the combined effect of the insertion loss and crosstalk on the OSNR is considered. Simulation results demonstrate that the EWOSA can identify approximately 0.18 dB lower worst-case OSNR than the existing formal worst-case analysis method in 8 × 8 mesh-based ONoC, and this improvement in OSNR accuracy becomes more apparent (up to 4.81 dB) when SOAs are deployed in ONoCs. Furthermore, the EWOSA can be used for OSNR optimization, owing to its rapid analysis speed and generality.

In this paper, the dual peak current limiting characteristics of superconducting fault current limiters (SFCLs) using dual iron cores were compared to each other. The SFCLs were connected in series between two coils (N1 and N2 ). However, the two coils were connected differently to the current source location. The dual peak current limiting characteristics and power burden of these SFCLs could be varied depending on design factors, such as the current source location between the two coils. Using a short-circuit simulation experiment, we compared and analyzed the operating status of the two superconducting elements and their peak current limiting characteristics based on the current source location. [ABSTRACT FROM AUTHOR]

In this paper, the transformer-type superconducting fault current limiter (SFCL) with additional circuit, which could limit the fault current through twice quench operations, was suggested. The suggested SFCL includes one primary winding, two nonisolated secondary windings wound on the same iron core, and two high-TC superconducting elements connected with each secondary winding. The advantage of the suggested SFCL is that it can perform the twice current limiting operations due to the transient amplitude of the fault current. Among its design parameters, the winding direction of another secondary winding comprising the additional circuit of the transformer-type SFCL or the nonisolated secondary winding is expected to affect its fault current limiting characteristics. To analyze the dependence of the fault current limiting operation on the winding direction of two nonisolated secondary windings, two limiting operational currents from its electrical equivalent circuit were derived. Through the fault current limiting tests for the suggested SFCL, the fault current limiting characteristics of the SFCL were discussed. [ABSTRACT FROM AUTHOR]

In this paper, the transformer-type superconducting fault current limiters (SFCLs) with common connection point between two secondary windings, which was similar structure to the previously suggested transformer-type SFCL with two triggering levels, was proposed and their current limiting characteristics were compared. The suggested transformer-type SFCLs consist of the primary winding and two secondary windings with common connection point. However, the current limiting operations through two triggering levels, which can be generally adjusted by the winding direction and the number of turns between two secondary windings, are affected by the application position of two high-TC superconducting (HTSC) elements into the transformer type SFCL with common connection point. To analyze the dependence of the current limiting operation on the application position of two HTSC elements, the short-circuit tests for the transformer-type SFCL with two different positions of two HTSC elements were carried out and their current limiting characteristics were compared from the point of view of the power burden and the accumulated energy of two HTSC elements comprising each transformer-type SFCL. [ABSTRACT FROM AUTHOR]

An optical network-on-chip (NoC) has attracted increasing attention with the advancement of silicon photonics technology due to the explosive growth in communication traffic in system-on-chip and the diminishing returns of miniaturized metal interconnect. Compared with the traditional metallic interconnect, the optical interconnect has superior effective bandwidth, transmission latency, and power consumption. In this paper, we establish an algorithmic optical router design framework to minimize the insertion loss, which is the loss of signal power resulting from the insertion of microring resonators and waveguide crossings. By incorporating system-level considerations on the topology, routing algorithm, and traffic pattern in the optical NoC, the proposed technique provides a rapid design environment for a wide range of application-specific optical NoC architectures with minimized optical signal power loss. [ABSTRACT FROM PUBLISHER]

In this paper, equivalent electric circuit models of a commercial 1.2-kW proton exchange membrane (PEM) fuel cell stack are proposed based on ac impedance studies. The PEM fuel cell stack was operated using room air and pure hydrogen (99.995%). Using electrochemical impedance spectroscopy (EIS) technique, impedance data were collected in the laboratory under various loading conditions. Impedance data were analyzed and circuit models developed using basic circuit elements like resistors and inductors, and distributed elements such as Warburg and constant-phase elements. A nonlinear least-square fitting technique is employed to obtain the circuit parameters by fitting a curve to the experimental impedance data. Two circuit models of the fuel cell, one for low and one for high currents are proposed. The average ohmic resistance for the whole stack is estimated to be 41 m\Omega. Double-layer capacitances are determined at anode and cathode at various current densities. As expected, cathode charge transfer resistance turns out to be much higher than the anode charge transfer resistance because of slower kinetics of the oxygen reduction reaction. At higher load currents, a significant increase in mass transfer resistance as well as low-frequency inductive effects is observed. These low-frequency inductive effects are recognized and modeled in the fuel cell models of this work. Finally, a semiquantitative analysis was used to determine the contribution of individual performance factors to the overall fuel cell voltage drop. The transient response of the fuel cell circuit models is simulated using MATLAB/Simulink and their performance is validated by comparison with experimental data. [ABSTRACT FROM PUBLISHER]

In this work, we address key design aspects of mobile wireless terminal chipsets with practical examples. Significant expansions in capability, in conjunction with market demands for compactness, reasonable price and longer battery life, place substantial pressure on handset component technologies. To achieve these mutually conflicting goals with available implementation technologies, specialized design skills are necessary for power saving, chip-to-chip interface and subsystem integration in mobile phone chipsets. The inter-related design and verification issues are discussed with lessons learned from our professional experiences in designing third-generation cellular modems, mobile digital TV, and mobile WiMax System-on-a-Chip development. [ABSTRACT FROM AUTHOR]

The flux-lock type superconducting fault current limiter (SFCL) uses the magnetic coupling between two coils connected in parallel with each other. This SFCL has the merit that both the resistance of high-TC superconducting (HTSC) element and the limiting current capacity can be simultaneously increased through the application of magnetic field into HTSC element. However, like other type of SFCLs using an iron core, unless the saturation of the iron core in the design is considered, the actual limited fault currents can be higher than expected as the saturation of the iron core occurs, and can lead to damage the electrical equipment of the power system. To analyse the dependence of the fault current in the flux-lock type SFCL on the fault angles, its electrical equivalent circuit with the magnetization branch was derived. From the electrical equivalent circuit, the fault current and the inner magnetic flux considering the fault angles as well as the design parameters such as winding direction and inductance ratio of two coils were calculated. The analysis results were compared with the experimental ones, and both the results agreed. [ABSTRACT FROM AUTHOR]