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Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device $V_{t}$ menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization ( $P_{r}$ ) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ferroelectric/metal/insulator/semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over >6 decades. In a CMOS circuit, due to CCM, low- $V_{t}$ pairs provide steeper subthreshold swing (SS) than high- $V_{t}$ pairs. Transient power/performance is also modeled, and it is shown that a DC-optimal NCFET design, employing broad junctions, CCM, and a low- $V_{t}$ NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.

In this paper we demonstrate a novel methodology to electrically test and characterize resistive random-access memory (RRAM) single bit devices for deep learning application. We extract critical device performance metrics for validating and optimizing fabrication processes which feed into yield learning. We adopt the algorithm-based bias condition search methodology and extract forming and switching voltage parameters without overdriving the devices. This test methodology can be used for Technology Development Learning Cycle in a research and development environment.

Recently, modular multi-level converters (MMC) are attracting attention as the next generation of high-capacity power converters. For the control method, PI control is widely applied. On the other hand, the deadbeat control and the model predictive control, which are known as a model based digital control methods, was applied to improve the tracking accuracy, and the superior characteristics have been reported for these methods. In this paper, a quasi multi-rate deadbeat control (QMDB control) with the PWM hold method based on FPGA based hardware controller for MMC was proposed. The advantages of the proposed method were verified through the simulations and the experiments.

In this paper, we propose a method to align time stamps for sensed data among multiple data logging devices. In the method, we use the timing signals from the global navigation satellite systems (GNSS) and inertial measurement units (IMU) that have a frame-synchronous-input. The frame synchronous input is an external input, and its value will be attached to sensed data as the timing label bit. In most of the data logging method, the timestamp is generated and attached to the data by its data logging device. However, the timestamps contain a clock jitter about 100 ppm or more due to the internal clock inferior quality in a low-cost devices. It is difficult to sample data continuously time interval being fixed and to attach timestamps with high reliability. Therefore, we estimate the actual sampling timing of sensed data measured by IMUs using the timing signals from a GNSS module. Our key idea is to utilize the fact that actual sensors' internal oscillator is slightly out of alignment with the precise clock, which can be provided by the navigation satellites. We applied the proposed method to 1 kHz sampling data obtained from a commercially available sensing module of several dollars equipped with a quartz crystal. We have confirmed that the proposed method improves the precision of such sampling timing from around 350 microseconds to 150 microseconds.

In this paper, we propose the extendibility of ultra-thin body and box (UTBB) devices to 7 and 5 nm technology nodes focusing on electrostatics. A difficulty in scaling traditional UTBB is the need for SOI scaling to about one fourth of the gate length. We propose a U-channel fully depleted silicon on insulator architecture that starts off with a thicker SOI (8–11 nm) and has a U-shaped channel enabled by a recessed metal gate. This device improves the electrostatics by increasing the overall gate length at fixed metal gate opening, mitigating drain field coupling to the source due to the recessed metal gate region and having thin SOI below the center of the device (4–5 nm). Modeling shows that good electrostatics can be maintained at small metal gate opening to enable pitch scaling. This device provides lower cost options for mobile and IOT technologies.

We demonstrate a CMOS-compatible, metal-oxide based Electro-Chemical Random-Access Memory (MO- ECRAM) for high-speed, low-power neuromorphic computing. The device demonstrates symmetric and linear conductance update, large on/off ratio and good retention while also withstanding high temperature treatments necessary for BEOL compatibility. Resistive switching in MO-ECRAM is observed with voltage pulses down to 10 ns and scales exponentially with voltage pulse amplitude, enabling parallel array operations without any selector/access devices. For the first time, we experimentally demonstrate fundamental techniques for fully- parallel array operations, stochastic update scheme and zero-shifting technique, and show a successful stochastic gradient descent algorithm demonstration in hardware using a MO- ECRAM array.

In this work, we investigate the statistical evolution from nano-conducting path generation to the switching-filament formation in ReRAM devices. We demonstrate the Gumbel statistics, a maxima-value distribution for switching-filament conductance as opposed to the minima-value Weibull model. In contrast to Poisson distribution for nano-path generation, we show the underlying spatial statistics is controlled by a binomial distribution as a result of filament-formation. The reorganization and conglomeration of interacting nano-paths or individual vacancies eventually leads to area-dependent single-filament formation, consistent with the Gumbel statistics. Our methodology provides the foundation for RRAM scaling as well as an essential tool for the development of RRAM technology.

Currently, modular multi-level converters (MMC) are attracting attention as the next generation of high-capacity power converters. For the control of the MMC, PI control is widely used. On the other hand, the deadbeat control and/or the model predictive control was applied as for the model based digital control method, and the superior characteristics were obtained. In this paper, a quasi multi-rate deadbeat control for MMC was proposed using a PWM hold method. Applying FPGA based hardware controller, instantaneous control calculation can be carried out which result in the ideal digital control feedback system. The advantages of the proposed method were verified through simulations and experiments.

In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.

Specialized hardware for deep learning using analog memory devices has the potential to outperform conventional GPUs by a large margin. At the core of such hardware are arrays of non-volatile-memory (NVM) devices that can perform the simple matrix operations needed for deep learning in parallel and in constant time. Several implementations can be found in the literature that use different materials as memory elements, including phase-change-memory (PCM), resistive-random-access-memory (RRAM), electrochemical-random-access-memory (ECRAM), and ferroelectric devices. While the current focus is to demonstrate functionality, there is an increasing concern about the reliability margins of this emerging technology. In this paper we will briefly describe operation and device requirements, and then focus on possible reliability exposure in terms of variability, stability and drift, retention and durability.

A power packet dispatching system for the robot arm operation is discussed. Recent wide-band-gap power semiconductor technology realizes high speed and low switching loss devices such as SiC and GaN. The power packet dispatching system is the power distribution system in which DC voltage is delivered with the information tag in the same power line. To include the information into the packet, switching speed of the switching device is desired over MHz range. SiC or GaN device is attracting solution to realize the power packet system. Six arm robot operation with the power packet dispatching system is designed and evaluated. Design concept is described to interface the power and the information in simultaneously. Realization of the proposed method was evaluated.

Using devices with well passivated interfaces and reduced electron trapping, it is demonstrated that significant interface-state generation occurs during PBTI stress in InGaAs MOS capacitors with Al 2 O 3 /HfO 2 /TiN gate stacks. These observations on capacitors imply that the impact of interface-state generation on mobility and subthreshold-degradation need to be monitored in III-V nFET in addition to electron trapping in the gate stack.

Strained-SiGe, with high-Ge-content, has recently drawn significant attention as an alternate p-channel option for advance FinFETs. Among various technological challenges, gate stack is so critical to enable high-performance FETs. In this paper, key process details of the optimized gate stacks in high-Ge SiGe, such as IL formation and passivation, are disclosed and feasibility of Vth tuning by an ultra-thin replacement metal-gate scheme down to 15nm LG is demonstrated, for the first time. Moreover, near ideal SS, excellent reliability and mobility at scaled EOTs are achieved, which has led to high transconductance devices with proper junction engineering. In addition, we demonstrate the most aggressively-scaled SiGe fins reported to date formed by 3D-Ge-condensation, exhibiting excellent short-channel characteristics.

In this paper, we report multi-threshold-voltage (multi-Vt) options for stacked Nanosheet gate-all-around (GAA) transistors. V t can be modulated through workfunction metal (WFM) thickness as well as the inter-nanosheet spacing (T sus ), the combination of which may be leveraged to increase the number of undoped V t offerings within a CMOS device menu relative to a FinFET CMOS device menu, which fundamentally does not have T sus as a V t tuning option. Hence we propose our multi-V t scheme by taking advantage of the unique structure of stacked GAA transistor.

Planar ultra-thin body and box (UTBB1–3) fully depleted silicon on insulator (FDSOI) devices have many advantages for future low-cost energy-efficient applications. However, process steps for scaling to ultra-thin FDSOI devices can be difficult to control, and extrinsic resistance can hinder any performance improvement. In this paper, we present a novel planar U-channel UTBB FDSOI device that can alleviate these problems.

In this paper, we discuss a technique for selective GeO x -scavenging which creates a GeO x -free interfacial layer (IL) on Si 1−x Ge x substrates. This process reduces interface trap density (N it ) and increases high-field hole mobility in Si 1−x Ge x pFETs. In addition, we identify the existence of electronic defect levels close to the Si 1−x Ge x band edges associated with the Ge surface concentration at the Si 1−x Ge x /IL interface. These electronic defects act as carrier scattering centers severely degrading the channel mobility and modulate the device threshold voltage. By successfully eliminating the GeO x component in the IL and electronic defects states at the Si 1−x Ge x /IL interface, high channel carrier mobility over a wide range of inversion carrier density in compressively-strained Si 1−x Ge x channel pFETs is demonstrated.

We demonstrate scaled high-Ge-content (HGC) strained SiGe pMOS FinFETs with very high short channel (SC) performance using a Replacement High-K/Metal Gate (RMG) flow, for the first time. A novel RMG gate stack process was introduced to create Ge-free interface-layer (IL) with excellent reliability and sub-threshold swing (SS) as low as 62mV/dec, the best reported to date for Si-cap-free SiGe FinFETs. We also present some structural details of the gate stack, for the first time. Short channel characteristics of HGC SiGe FinFETs have also been studied for various fin widths. Compared to our earlier RMG work, improved I/I free process with ultra-thin spacers has led to considerable R on and R ext reduction. As a result, we have demonstrated very high SiGe performance with I on =0.45mA/μm at I off =100nA/μm at V dd =0.5V for L G =25nm, matching our record for gate-first SiGe FinFETs and outperforming the gate-first results at such LG.

FinFETs with strained-SiGe channel have recently drawn significant attention due to their built in uniaxial strain, higher mobility and better reliability over conventional Si FETs. Research on pure Ge has been the major focus of many institutes over the past few years. However, with high-Ge-content (HGC) SiGe one can benefit from competitive or better performance over pure Ge and overcome the thermal budget constraints required for Ge. In this paper, we briefly review our latest advancements in high-Ge-content strained-SiGe FinFETs featuring gate first and Replacement HK/MG (RMG) flows with record mobility and short-channel performance to extend the roadmap for advanced FinFET and FDSOI generations.

We demonstrate high-performance (HP) High-Ge-Content (HGC) SiGe pMOS FinFETs with scaled EOT and improved junction. For the first time, SiGe FinFET EOT scaling down to ∼7A has been achieved. In addition, improved junction and series resistance has been demonstrated for HGC SiGe, by a proper choice of spacer thickness and interface-layer as well as hot ion-implant (I/I), resulting in significant R on reduction down to 250 and 200Ω.µm, respectively. We report the highest “SiGe extrinsic g m ” reported to date with g m, LIN =0.5mS/µm and g m, SAT =2.7/2.5mS/µm at V DD =1.0/0.5V, the highest HGC SiGe I on =0.45mA/µm at fixed HP I off =100nA/µm at V DD =0.5V and the highest pMOS FinFET performance reported to date at sub-35nm L G .

High-Ge-content (HGC) SiGe FinFETs in a “replacement High-K and metal-gate” (RMG) process flow and with aggressive EOT scaling are demonstrated, for the first time. HGC SiGe pMOS FinFETs with high-mobility, record-low RMG long-channel SS=66mV/dec and great short-channel characteristics down to L G =21nm have been demonstrated. Gate stack and transport properties down to sub-4nm fin widths (W FIN ) have been also studied for the first time. We demonstrate excellent RMG mobility and reliability at aggressive EOT∼7A, and excellent μ eff =220cm2/Vs at N inv =1013 for fins with W FIN ∼4nm, outperforming state-of-the-art devices at such dimensions and providing very promising results for FinFET scaling for future high-performance FinFET generations.

Bias Temperature Instability (BTI) is a tremendous reliability concern for deeply scaled CMOS technologies, and is the limiting mechanism for further inversion layer thickness (Tinv) scaling for future nodes [1]. Replacement Metal Gate technologies are of particular concern, since the gate stack is not exposed to the high temperature source/drain anneals. We have identified four strategies for reducing BTI in Replacement metal gate technologies: Rapid Thermal Anneal (RTA) optimization, optimization of the HfO2 layer thickness, introducing a gate dielectric dopant for NBTI reduction, and effective Work Function tuning. Judiciously combining these four techniques enable further Tinv scaling for 10 nm and below.

We identified unique device width and length dependencies of Vt for FinFET Replacement Metal Gate (RMG). Choice of fill metal is important to obtain a flat Vt-Wdes trend. We proposed a new model for Vt-Lg roll-up for High-k last RMG and demonstrated a flat Vt-Lg trend via optimization of High-k and MOL films based on the understanding.

Continued scaling of semiconductor devices in logic and memory applications requires the introduction of high-k (HK) dielectrics to enhance the capacitance density while maintaining a low leakage. Of particular concern in DRAM memory applications is the so called `dielectric relaxation current', which is significantly enhanced with HfO2 dielectrics as compared to SiO2. In this paper, it is shown that these relaxation currents arise from electron trapping/detrapping by/from oxygen vacancy defects in the HfO2 dielectric from/to the contact electrodes. This understanding is utilized to minimize `dielectric relaxation currents' by optimizing the defect structure in the HK dielectric. By creating trap-free dielectric films with N or La doping, we show that substantial reductions in the relaxation currents can be achieved. For the first time, it is demonstrated that a HK dielectric stack formed as a result of these treatments can have reduced relaxation currents similar to SiO2, thus providing a pathway to solving a fundamental paradigm associated with HK dielectrics that has persisted for several years.

We present a fully-integrated SOI CMOS 22nm technology for a diverse array of high-performance applications including server microprocessors, memory controllers and ASICs. A pre-doped substrate enables scaling of this third generation of SOI deep-trench-based embedded DRAM for a dense high-performance memory hierarchy. Dual-Embedded stressor technology including SiGe and Si:C for improved carrier mobility in both PMOS and NMOS FETs is presented for the first time. A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability.

With the introduction of High-k, metal gates and alternate substrates into the gate-stack at the 45nm and 32nm technology nodes, Bias Temperature Instability (BTI) phenomena have had to be included into the chip design modeling. In this paper, we explore BTI trends with High-k transistors in manufacturing ready CMOS processes with gate last and gate first type process flows. In both flows, Positive Bias Temperature Instability (PBTI) is a strong function of the interface and High-k thickness, with aggressive interface scaling having significant adverse reliability implications. Negative Bias Temperature Instability, on the other hand, is strongly dependent on the quality of the interface and its nitrogen content. The introduction of germanium into the Si channel is found to significantly improve NBTI. With recovery effects being strong in both NBTI and PBTI, AC BTI models in realistic circuit designs are critical to accurately evaluate the BTI lifetime of chips.

Experimental reliability trends indicate that t inv -scaling with HKMG stacks remains challenging because NBTI, PBTI and TDDB reliability margins rapidly decrease with decreasing t inv values and increasing gate leakage current. A case is made that these observed trends arise from the layer structure and the materials properties of the SiO(N)/HfO 2 dual dielectric. Therefore, fundamental reliability limitations appear to increasingly impact HKMG stack scaling.

Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with T inv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

We demonstrate a novel “remote interfacial layer (IL) scavenging” technique yielding a record-setting equivalent oxide thickness (EOT) of 0.42 nm using a HfO 2 -based MOSFET high-к gate dielectric. Intrinsic effects of IL scaling on carrier mobility are clarified using this method. We reveal that the mobility degradation observed for La-containing high-к is not due to the La dipole but due to the intrinsic IL scaling effect, whereas an Al dipole brings about additional mobility degradation. This unique nature of the La dipole enables aggressive EOT scaling in conjunction with IL scaling for the 16 nm technology node without extrinsic mobility degradation.

Damascene gate process enhances the drivability in shorter gate length region, as compared to conventional gate 1st process for pFETs with compressive stress SiN liner and embedded SiGe. The origin of the gate length effect is investigated for the first time by using the UV-Raman spectroscopy. Moreover, the relationship between channel strain and gate width for damascene gate pFETs is analyzed and the effect is also demonstrated. It is found that channel strain is considerably enhanced in shorter gate length and narrower gate width by the combination of damascene gate process and stress enhancement techniques.

This paper investigates a replication process using the organic-inorganic hybrid material. The condition of heat treatment was determined on the basis of the hardness and transmission measurements. 100 repeated imprints were demonstrated using the replicated mold and achieved good fidelity.

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12A) for BE nFET devices to-date, consistent with simulations showing the need for ≪14A T inv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin Tinv (≪13A) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.

The impacts of interfacial layer (IFL) thickness and crystallinity of HfO2/IFL bi-layer on electrical properties were clarified using synchrotron radiation photoemission spectroscopy (SRPES) and electrical measurements of nFETs (HfSix/HfO2) and pFETs (Ru/HfO2) including BTI. It was found that crystallization of HfO2 causes significant degradation in electron mobility and PBTI, whereas the impacts on hole mobility and NBTI are negligible. The SRPES measurement revealed that the crystallization temperature depends on HfO2 thickness. We also found that the IFL thickness is the dominant factor for both electron mobility and PBTI. Therefore, a careful optimization of the HfO2/IFL bi-layer is indispensable. We proposed a novel technique for controlling the bi-layer thickness and demonstrated dual metal CMOS devices with high mobility and high reliability even by a post high-k process lower than 500degC for the very first time.

Sub-1nm EOT and high electron mobility were realized at the same time with HfSix/HfO2 gate stacks. It was revealed that there exist two mobility degradation modes depending on the HfO2 thickness and the HfSix composition. One is the crystallization in the thick HfO2 case (Tinv > 1.6 nm). The other is the Hf penetration into the interfacial layer with the Si substrate (bottom-IFL) in the thin HfO2 case (Tinv < 1.6 nm) for the Hf-rich electrode. We have demonstrated that carefully optimizing the HfO2 thickness and introducing a novel "Si extrusion" process from the HfSix electrode can suppress both modes. As a result, a high electron mobility equivalent to n+poly-Si/SiO2 (248 cm2/Vs @ Eeff = 1 MV/cm) was obtained at the sub-1nm EOT region for the very first time. The successful scaling together with a well-controlled Vth roll-off led to an extremely high Ion of 1165 muA/mum (@ Ioff = 81 nA/mu) at Vdd = 1.0V for a 45nm gate nMOSFET

We have developed a dual metal gate CMOS technology with HfSix for nMOS and Ru for pMOS on HfO2 gate dielectric. These gate stacks show high mobility (100% of universal mobility for electron, 80% for hole at high fields) down to Tinv of 1.7 nm and symmetrical low Vt equivalent to poly-Si/SiO2. As a result, high drive currents of 780 muA/mum and 265 muA/mum at Ioff = 1 nA/mum are achieved for Vdd = 1.0 V in Lg = 60 nm nMOS and pMOS, respectively We have applied the mobility enhancement technology to the Ru/HfO2 pMOS by utilizing (110)-substrate. As a result, an excellent drive current of 400 muA/mum (151% improvement over (100)-p+poly-Si/SiO2) is achieved

We have developed a high performance pMOSFET with ALD-TiN/HfO2 gate stacks on (110) substrate using gate last process at low temperature. High work function and low gate leakage current are obtained. An extremely high mobility equivalent to P+ poly-Si/SiO2 on (110) substrate (171 cm2/Vs at 0.5 MV/cm) is achieved with ALD-TiN/HfO2 on (110) substrate in the thinner Tinv region of 1.7 nm. Vth roll-off characteristics are well controlled down to 50 nm. A high drive current of 380 uA/um at Ioff = 1 nA/um is achieved at Vdd = 1.0 V. The drive current of ALD-TiN/HfO2 gate stack on (110) substrate is improved 1.4 times compared with (100) substrate and 2.4 times compared with P+ poly-Si/SiO2 on (100) substrate.

We propose HfSix/HfO2 gate stacks as the most suitable combination for high performance nMOSFETs. An equivalent work function (WF) to n+poly-Si was obtained by controlling Hf/Si ratio of the electrode. The highest electron mobility ever reported was achieved in the thinner Tinv region down to 1.6 nm by low temperature process without using plasma nitridation both for metal and high-k fabrication. As a result, the extremely high drive current of 1.25mA/mum at off-state leakage of 1 nA/mum and low gate leakage current of 0.3A/cm2 were obtained at Vdd = 1.3V with 65 nm gate length nMOSFETs without strain enhanced technology

CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6 nm were obtained for the nFETs and pFETs. The further integration of pFETs on (110) substrates contributed to a higher drive current of 830 muA/mum. These performances were realized under low gate leakage currents of 0.03 A/cm2 and below

A distributed-feedback dye laser was fabricated by use of alternate spin-coating of a high and a low refractive-index polymer. The laser was emitted from the surface of the dye-doped polymeric multilayer at the designed wavelength.