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2. A 180 MHz multiple-registered DRAM for low-cost 2 MB/chip secondary cache

Author

Seiji Sawada, Akira Yamazaki, Masaki Kumanoya, Takayuki Miyamoto, M. Itoh, Yasuhiro Konishi, N. Watanabe, Y. Murai, and Hisashi Iwamoto

Subjects
Dynamic random-access memory, Hardware_MEMORYSTRUCTURES, CPU cache, Computer science, business.industry, Pipeline burst cache, CAS latency, law.invention, Read-write memory, Smart Cache, law, Cache, business, Dram, Computer hardware
Abstract

A Multiple-registered DRAM is described for 2 MB/chip secondary cache. 64 registers per bank of the RAM enable the data transfer from 64 dynamic memory cells to the registers simultaneously, realizing 180 MHz cache fill operation. The area increase with the architecture is only 5.4% over the conventional DRAM, which contributes to realize low-cost high-performance cache systems. >

Published
2002
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