Search

Ferroelectric field-effect transistors (FEFETs) are an important candidate for emerging nonvolatile memory applications but suffer from a lack of physical understanding of the device operation. Previous FEFET models utilized the Preisach model of ferroelectrics and do not accurately capture the physics of the FEFET that the majority of the polarization charge is screened by trapped charge at the interfaces. We propose an empirical model for FEFETs, which also considers screening of ferroelectric polarization. The screening charge is modeled as a dissipative (leakage) current across the baseline MOS gate-stack. The proposed model is calibrated using the experimental data of p-type ZrO2 FEFETs and unravels the weak electrostatic coupling between the ferroelectric polarization and semiconductor channel charge. In addition, the model captures the memory window discrepancy between the charge–voltage characteristics and current–voltage characteristics observed in the experimental data, provides new insight into the ferroelectric device, and is well-suited for use as a compact model implementation of FEFETs. [ABSTRACT FROM AUTHOR]

While the theoretical maximum of the memory window $\Delta {V}_{t}$ in a ferroelectric field-effect transistor (FEFET) is $2{E}_{C}{t}_{F}$ , ${E}_{C}$ and ${t}_{F}$ being coercive field and FE thickness, respectively, experimentally $\Delta {V}_{t}$ is observed to be much less than that, even in the case of complete polarization switching in the ferroelectric layer. This occurs because trapped charges in the gate oxide stack partially or completely screen the ferroelectric polarization, only a fraction of which gets “electrostatically” reflected in the semiconductor channel. In this article, we provide a generalized experimental framework to quantify the efficiency of practical FEFETs in converting the switched ferroelectric polarization into the memory window. To that end, we propose three efficiency metrics: 1) switched ferroelectric polarization $\Delta {P}_{F}$ to memory window conversion ratio, $\eta _{MW}=\Delta {V}_{t}/\Delta {P}_{F}$ ; 2) switched ferroelectric polarization to the semiconductor charge ($\Delta {Q}_{S}$) conversion efficiency or the charge conversion efficiency $\eta _{c}=\Delta {Q}_{s}/\Delta {P}_{F}$ ; and 3) the ratio of memory window to the width of polarization versus gate voltage hysteresis characteristics ($\Delta {V}_{P}$) or the voltage conversation efficiency $\eta _{V}=\Delta {V}_{t}/\Delta {V}_{P}$. We measure and compare these efficiency metrics in n-type and p-type FEFETs, fabricated in different facilities by different groups. In all the cases, we find that the maximum values of memory window efficiency $(\eta _{MW})_{max}$ , charge conversion efficiency $(\eta _{c}$) $_{max}$ , and voltage conversion efficiency ($\eta _{V}$) $_{max}$ are in the range: 2.5–5.5 Vm2/C, 4%–10%, and 5%–20%, respectively. [ABSTRACT FROM AUTHOR]

Despite tremendous interests in ferroelectric field-effect transistors (FEFETs) for embedded, data-centric applications, the fundamental trade-offs between memory window (MW) and write voltage to optimize performance remains poorly understood. To that end, we fabricated ferroelectric (FE) $ZrO_{2}$ based, p-type FEFETs and studied the impacts of FE and the interfacial oxide layer (IL) thicknesses ($t_{FE}$ and $t_{IL}$ , respectively) on device performance. We observe that a decrease of $t_{FE}$ and $t_{IL}$ reduces not only write voltages for erasing and programming, but also the memory window. A quantitative analysis of these results offers the following insights and guidelines for FEFET design: to decrease write voltages, all of $t_{FE}$ , $t_{IL}$ and coercive field of FE needs to decrease, and to compensate for the subsequent decrease in MW, the polarization of the FE needs to be increased - notwithstanding the fact that the reliability implications of the magnitude of FE polarization still need to be understood. [ABSTRACT FROM AUTHOR]

To scale the ferroelectric random access memory (FeRAM) technology toward 28 nm or beyond, it is critical to develop stacked capacitor (with sufficient surface area) to allow good sense margin for the 1-transistor- 1-capacitor (1T1C) bit cell. Therefore, to enable 3-D integration in back-end-of-line (BEOL) process, it is essential to optimize the fabrication recipes in low-thermal budget (< 400 °C). In this regard, we investigated the low-temperature process for ferroelectric Hf0.5Zr0.5O2 (HZO) capacitor with the plasma-enhanced atomic layer deposition (PEALD). It was found that, with sufficient annealing time (>50 s) in low temperature (~ 350 °C), the ferroelectric properties of HZO could be fully manifested. No degradation is shown in the remnant polarization (Pr) under the optimized low-temperature process. Furthermore, the retention/endurance characteristics with different Pr states were measured to determine the minimally required write voltage. Finally, the SPICE simulation is conducted to evaluate the sense margin of the projected 28-nm 1T1C array with stacked cylindrical capacitors using the measured Pr drift behavior over time. [ABSTRACT FROM AUTHOR]