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As society gradually relies on technologies to prevent dangers and detect the environment, the processing of data transmission and analysis becomes important. In recent years, firefighters are sacrificed during rescue missions. Even with the high-tech equipment in the current era, the lives of firefighters are not prevented in the fire scene. Thus, this research designs and develops an alarm system for hospitals and schools. The Message Queuing Telemetry Transport (MQTT) technology and fire sensors are utilized and integrated to extract the conditions of the environment. In the system, the subscriber server collects the data on a personal computer. Also, the website and database server monitor the wards in a hospital. Integrating and designing the systems help to understand the emergent situation.

Students cheating in exams destroys the fair principle of evaluation and affects the normal teaching order of the school. Therefore, the examination cheating detection has the vital significance. The existing cheating detection methods have disadvantages such as insufficient modeling accuracy for students, lag in cognitive diagnosis, difficulty in detecting multi-source plagiarism and low accuracy. In order to solve the disadvantages of traditional methods, this paper proposes a method for detecting cheating in multi-index examinations based on feed-forward neural network. This paper first proposes RAE algorithm which combines linear regression and EM algorithm for students' cognitive diagnosis. We use RAE algorithm and LSTM neural network to obtain the knowledge point mastery degree of each student based on the history problem solving and the knowledge point mastery degree based on the exam problem solving. Then, according to the information of students' cognitive level, seat distribution in the examination room, students' habit of guessing answers at normal times, similarity of examination papers, etc., we get several indicators to judge whether students cheat. Finally, we take various indicators obtained through various methods as characteristics and use feed-forward neural network to classify whether students cheat or not. The experimental results show that the accuracy and recall of this method are significantly higher than those of several popular methods.

This paper provides an efficient transportation method using connected car technology. Based on shared information among vehicles, the method can provide smart navigation by two separated path planning and traffic prediction algorithms. The plan planning algorithm will generate the fastest path while the vehicle is moving to the destination, and the prediction algorithm will dynamically update the navigation cost of each street segment from intersection to intersection.

This paper reviews recent advances in in-situ and in-field techniques for monitoring and compensating aging in digital integrated circuits. For pipelines, we introduce an approach that combines circuit reconfiguration and voltage scaling down to so-called zero temperature coefficient voltage. This can directly monitor the delays of critical paths robustly against temperature variation. For SRAM circuits, we introduce new column and row peripheral circuits that can in-situ sense threshold voltage of each of six transistors in every bitcell, accurately against temperature variation in field post system deployment. We also introduce a software framework that can extract microarchitecture/circuit-level information from sensing results. With these techniques, we can exercise aging compensation schemes that can pin-point the components that undergo the worst-case aging effects. These monitoring and compensation techniques can contribute to the implementation of in-field reliability management. With such scheme a chip periodically and opportunistically enters a maintenance session. This enables each chip achieve near-optimal performance and energy-efficiency under a reliability envelope without imposing the design-time worst-case margin.

The integration of Mobile Edge Computing(MEC) with the Radio Access Network(RAN) has arisen as a futuristic technology. It offers the cloud-computing capabilities and high-speed wireless transmission to close to User Equipment(UEs) by deploying MEC servers on the Base Stations(BSs) in Ultra Dense Network(UDN). Mostly current research mainly focus on that the MEC server is a coadjutant to offload the computational tasks and reduce the energy consumption of UEs. However, the heterogeneity of servers and the agglomeration effect of users bring new challenge for the fair resource sharing and load balancing among MEC-BSs. In this paper, to efficiently relieve the unfairness of MEC-BS servers and utilize the whole computing resources, we envision a MEC collaborative architecture to achieve the resource sharing among MEC-BSs in UDN. Our design aims at reducing the time consumption of all tasks, where multiple weight and number of tasks can be delivered to different servers at random. We consider the time delay, resource consumption and the state of wireless channel to establish the system model and design an optimal model based on the transfer time and computation time consumption. Finally, we conduct the simulations of optimal task collaboration mechanism to evaluate the performance. The simulations result demonstrate a better performance improvement of the proposed strategy over the simply approaches in terms of average time consumption of per task and rate of tasks successfully completed.

Today's microprocessors and Systems-on-Chip are thermally limited. Many, therefore, employ dynamic thermal management (DTM) to maximize performance under a reliability constraint. Accurate thermal monitoring is critical as temperature underestimation can hurt reliability by excessively aging devices and overestimation can hurt performance by unnecessarily throttling computing components. Placing temperature sensors close to potential hotspots can help accuracy, but it is non-trivial as hotspots often form inside digital blocks consisting of densely placed digital cells. Large sensors can disrupt cell placement thereby increasing wire lengths and circuit delays. Furthermore, the sensor needs to operate from the same digital power grid as the circuit, one that can be scaled down to near-threshold regime via dynamic voltage scaling. Absent this ability, a separate power grid and dedicated supply voltage for the sensors further increases area overhead. In this paper, we present a sensor circuit that is compact and deeply voltage-scalable and can be embedded among digital cells with little disruption. Simulation results show that it achieves a comparable accuracy to other compact sensor circuits for DTM.

Visual SLAM in low illumination scenes remains a considerably challenging task since the available amount of appearance information frequently stays insufficient. To tackle with this problem, we propose a novel SLAM framework by using both appearance information and thermal information, which possesses illumination-free recognizable contents, in a flexible manner. The key idea is to continuously update a RGB-T map, which contains both RGB and thermal map points to implement location and mapping. More specifically, in our SLAM system, we detect features in both RGB and thermal images and combine them together to update the RGB-T map and implement simultaneous location and mapping. Both quantitative and qualitative results demonstrate the effectiveness of our framework, especially under low illumination environments.

Physically unclonable function (PUF) is one of the critical security primitives for key generation and storage. The key challenge in building a PUF is to achieve high robustness against noise, temperature/supply voltage (VDD) variations and device aging with low cost. This paper presents a technique to transform a pre-existing SRAM array into an analog PUF by configuring the access transistors in a 6T-SRAM bitcell into a pair of threshold voltage (Vth) sensors and comparing their outputs. The proposed analog PUF circuit achieves significantly better robustness than conventional SRAM-based PUFs using reset states while maintaining the benefit of hardware reuse: low area overhead. Test chips are prototyped in a 65nm CMOS to verify the randomness, uniqueness, and robustness of the proposed design.

This paper presents a novel microcontroller-system-on-chip (μC-SοC) for pervasive sensing systems, with a 6T SRAM instruction cache dynamically transformable to an ambient temperature sensor and physically unclonable function (PUF). As those sensing and PUF operations are performed in a duty-cycled manner in targeted systems, the proposed transformation can save silicon area, e.g., by ∼9.8X as compared to dedicated sensor and PUF circuits that achieve comparable robustness with our temperature sensor and PUF. Specifically, the temperature sensor achieves −0.5/+1.5°C error with one-point calibration and 0.46°C/100mV power supply sensitivity; the PUF passes applicable NIST tests, achieves 0.97% unstable bits and 0.62% BER with TMV and comparator-input-swapping.

This paper presents novel 6-T SRAM register file (RF) circuits and in-field framework for managing chip's lifetime after deployment. Our proposed RF circuits can in-situ sense threshold voltages (V t ) of all six transistors of every bitcell in an RF robustly against temperature variations. This allows us (1) to monitor aging effects of both NMOS and PMOS such as negative and positive bias temperature instabilities (NBTI, PBTI) and (2) to monitor those in the post deployment condition where environmental parameters, notably temperature, cannot be easily controlled. Using these sensed V t 's, our proposed post-deployment framework can estimate critical circuit-level parameters of an RF such as data retention voltage (DRV) and read access time (T ACC ). After chip's deployment, our proposed sensing circuits and framework can be periodically (e.g., every month) exercised to diagnose the reliability of an RF through chip's lifetime. We can use the results of the diagnosis to potentially trigger countermeasures. The area overhead of adding our proposed sensing capability to a 32×32b RF is 8.5%.

SRAM register files have sensitive circuitry and often operate with high switching activity and at high temperature. This makes them particularly vulnerable to aging by negative-bias temperature instability (NBTI) degradation of their PMOS devices. We propose a technique to sense this aging degradation; it is an in-situ technique sensing the threshold voltage (V t ) of PMOSs directly in bitcells, and can operate in-field, thanks to the ability to sense V, robustly across temperature and voltage variations. This technique can be foundational for several dynamic reliability management (DRM) approaches, including: 1) sensing V, values periodically (e.g., every several months) for evaluating the amount and the rate of NBTI degradation; 2) sensing V, differences between two PMOSs in a bitcell to determine their strength skew and to estimate the minimum functional voltage (V MIN ) degradation; and, 3) using the skew information across bitcells to create recovery vectors [1], which can be used to recover the aged PMOSs and thereby rebalance the skews. Existing in-situ techniques using ring oscillators [2, 3] or current sensors [4] to sense bitcell reliability and performance cannot support in-field operation, which is a critical issue for DRM since it is impractical to control environmental parameters, particularly temperature, during sensing.

In this paper, we propose a new deep learning network "GENet", it combines the multi-layer network architec- ture and graph embedding framework. Firstly, we use simplest unsupervised learning PCA/LDA as first layer to generate the low- level feature. Secondly, many cascaded dimensionality reduction layers based on graph embedding framework are applied to GENet. Finally, a linear SVM classifier is used to classify dimension-reduced features. The experiments indicate that higher classification accuracy can be obtained by this algorithm on the CMU-PIE, ORL, Extended Yale B dataset.

Both time synchronization and localization are critical issues for wireless sensor networks (WNSs) especially for Underwater Sensor Networks (USNs). In this paper, we have proposed an ameliorated joint synchronization and localization (AJSL) algorithm for 3D USNs using iterative weighted least square (IWLS) estimator. This algorithm takes advantage of projection technique with measurable depth information and inherent relationship between synchronization and localization. The closed-form expression of mean square error (MSE) is also derived and facilitates performance evaluation. Numerical results suggest that the proposed joint algorithm outperforms traditional separated approaches with the same communication cost and the joint scheme with less output latency.

On-chip temperature sensors are key building blocks for the thermal management of multi-core microprocessors. The sensors are embedded at multiple locations in a microprocessor and monitor temperatures that are used to manage the operation of the microprocessor under local and global thermal constraints. While existing sensors achieve impressive area and accuracy, emerging technology trends such as multi-core architectures, 3D integration, tri-gate devices, and low-voltage operation demand even better sensors with difficult-to-meet requirements. Those requirements are three-fold: 1) Sensors need to be area efficient. By increasing the number of cores and hot spots, there are more locations that require thermal monitoring. To reduce the overhead, the sensor footprint needs to be minimized. A compact footprint is further critical for design flexibility, as the exact sensor locations (e.g. near hot spots) are often only identified in later stages of the design process [1]. 2) Sensors need to have low calibration cost, while achieving sufficient accuracy. The requirements of

In this paper, a harmonic rejection mixer architecture capable of operating for a wide range of LO frequencies is demonstrated. The mixer can be configured to suppress any particular harmonic of the LO or multiple harmonics simultaneously. The level of suppression of each harmonic is controlled by a set of independent gain and phase tuning parameters. Feasibility of extension of this concept to higher order harmonics is also demonstrated. A proof-of-principle prototype has been designed and fabricated in a 45nm SOI technology. Experimental results demonstrate an operation range of 0.5GHz to 1.5GHz for the LO frequency while offering harmonic rejection better than 55dB for the 3rd harmonic and 58dB for the 5th harmonic across LO frequencies. The mixer consumes 17mW of power from a 1V power supply while occupying an area of 0.352mm2.

Time synchronization is a critical issue in distributed systems especially for wireless sensor networks (WSNs). Most existing synchronization algorithms, such as Reference Broadcasts Synchronization (RBS), Time-sync Protocol for Sensor Networks (TPSN), Flooding Time Synchronization Protocol (FTSP) and etc., assumed instantaneous communication between the pair of nodes intended for synchronization, which is however hard to implement in high latency systems. Time Synchronization for High Latency networks (TSHL) is another algorithm to address this problem for short range networks and ideally assumes constant clock skew during synchronization, which is impractical for longer communication distance with higher latency and viable clock skew. By analyzing the compensating error of TSHL, we proposed a novel frequency tracking synchronization algorithm for high latency networks. Numerical results suggest that the proposed algorithm works well for variable clock skew and outperforms TSHL scheme.

Identifying the semantic relatedness of two words is an important task for the information retrieval, natural language processing, and text mining. However, due to the diversity of meaning for a word, the semantic relatedness of two words is still hard to precisely evaluate under the limited corpora. Nowadays, Wikipedia is now a huge and wiki-based encyclopedia on the internet that has become a valuable resource for research work. Wikipedia articles, written by a live collaboration of user editors, contain a high volume of reference links, URL identification for concepts and a complete revision history. Moreover, each Wikipedia article represents an individual concept that simultaneously contains other concepts that are hyperlinks of other articles embedded in its content. Through this, we believe that the semantic relatedness between two words can be found through the semantic relatedness between two Wikipedia articles. Therefore, we propose an Editor-Contribution-based Rank (ECR) algorithm for ranking the concepts in the articlei¦s content through all revisions and take the ranked concepts as a vector representing the article. We classify four types of relationship in which the behavior of addition and deletion maps appropriate and inappropriate concepts. ECR ranks those concepts depending on the mutual signed-reinforcement relationship between the concepts and the editors. The results reveal that our method leads to prominent performance improvement and increases the correlation coefficient by a factor ranging from 4% to 23% over previous methods that calculate the relatedness between two articles.

A new T-model has been developed to accurately simulate the broadband characteristics of on-Si-chip spiral inductors, up to 20 GHz. The spiral coil and substrate RLC networks built in the model play a key role responsible for conductor loss and substrate loss in the wideband regime, which cannot be accurately described by the conventional /spl pi/-model. Good match with the measured S-parameters, L(/spl omega/), Re(Z/sub in/(/spl omega/)), and Q(/spl omega/) proves the proposed T-model. Besides the broadband feature, scalability has been justified by good match with a linear function of coil numbers for all model parameters employed in the RLC networks. The satisfactory scalability manifest themselves physical parameters rather than curve fitting. A parameter extraction flow is established through equivalent circuit analysis to enable automatic parameter extraction and optimization. This scalable inductor model will facilitate optimization design of on-chip inductor and the accuracy proven up to 20 GHz can improve RF circuit simulation accuracy demanded by broadband design.