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In this paper, we propose a bidirectional gate driver on array (GOA) circuit design based on indium gallium zinc oxide (IGZO) thin-film transistor (TFT) to support time-division driving method (TDDM) for in-cell touch displays. The proposed circuit allows the touch panel to pause the display for touch sensing operations to achieve a touch reporting rate as twice as the frame rate of a display. A dual low-level maintaining unit design is used to suppress influence of the threshold voltage shift of TFTs through alternately turning on the devices. Owing to recovery of threshold voltage shift under negative bias, this design can maintain stable performance during long time operation. A narrow border 6.5” in-cell LCD panel of 90 Hz display with a 180 Hz touch reporting rate is finally demonstrated.

This paper presents a compact model for organic thin-film transistors fabricated in the staggered or coplanar device architecture which includes short-channel effects related to the potential barrier in the channel region, which manifest themselves as threshold voltage roll-off, drain-induced barrier lowering, and subthreshold swing degradation. Furthermore, the effect of non-linear injection due to a work-function mismatch between the source/drain contacts and the semiconductor is considered. The model includes a charge-based capacitance model considering overlap and fringing regions in short-channel multi-finger layout structures. Extensions include a model for drain-current variability, low-frequency noise and non-quasistatic effects. The introduction of physically meaningful fitting parameters provides a high degree of flexibility to the model. The equation package is verified using the results of measurements performed on transistors fabricated on flexible substrates and is available in Verilog-A for an efficient circuit simulation on different design platforms.

In this work, the polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with double gates and nanosheet (NSH) channel structures were fabricated to investigate the impact of NSH channel thickness (tSi) ranging from 15 nm to 2 nm on device performance and reliability. Thinning tSi from 15 nm to 10 nm resulted in improved control of channel potential by the gate voltage, leading to a decreased threshold voltage (VTH) and subthreshold swing (SS). However, further reduction of tSi to 5 nm, while continuing to decrease SS, caused an increase in VTH due to the grain size reduction and quantum confinement (QC) effects. Lastly, reducing tSi to 2 nm resulted in an increase in both SS and VTH mainly due to the QC effect. In terms of reliability, under a fixed positive gate bias stress condition, thinning tSi enhanced the electric field stress, leading to more severe device damage. However, due to the enhanced ability of gate voltage control over the channel potential and the buried channel effect on electron transport resulting from thinning the channel thickness, there exists an optimal range between 10 nm and 5 nm for the selection of tSi in terms of the degradation of VTH, SS, and on-state current. Consequently, it is evident that for transistors utilizing NSH channels, the selection of tSi is not a case of “the thinner, the better.” This finding highlights the need to consider the optimal tSi range between 10 nm and 5 nm, balancing the performance and reliability aspects of the device design. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate the effectiveness of nitrogen plasma treatment on the formation of low-resistive source/drain (S/D) in self-aligned (SA) oxide thin-film transistors (TFTs) using a high-mobility oxide semiconductor (OS), In-Ga-Zn-Sn-O (IGZTO). The nitrogen plasma treatment was more effective at reducing the sheet resistance ( ${R} _{\mathrm{ sheet}}$ ) of IGZTO films than the commonly used argon plasma treatment. Furthermore, ${R} _{\mathrm{ sheet}}$ for nitrogen-plasma-treated IGZTO films remained low, even when the RF power and radiation time during the plasma treatment were increased when the minimum ${R} _{\mathrm{ sheet}}$ was achieved. The same trends were also observed in OS films with different compositions, such as In-Ga-Zn-O and In-Sn-Zn-O. These results indicate that nitrogen plasma treatment is effective for achieving a reduction of ${R} _{\mathrm{ sheet}}$ for various OS films with a wide process window regarding plasma processing parameters. The advantages could be attributed to the smaller sputtering effect on the OS films due to the lower mass of nitrogen ions than argon ions, which was verified by X-ray reflectivity and X-ray photoelectron spectroscopy analyses. For further validation, SA IGZTO TFTs with a channel length ( ${L}$ ) of 3 to 100 $\mu \text{m}$ were fabricated with nitrogen or argon plasma treatment. The width-normalized parasitic SD resistance ( $R_{\mathrm{ SD}} {W}$ ) with the nitrogen plasma treatment was determined to be 11.3 $\Omega \cdot $ cm, which was ca. 40% lower than that with the argon plasma treatment. This improvement in $R_{\mathrm{ SD}} {W}$ resulted in higher mobility ( $\mu $ ) in the nitrogen-plasma-treated SA IGZTO TFTs. A nitrogen-plasma-treated SA IGZTO TFT with $L=10\,\,\mu \text{m}$ exhibited a high $\mu $ of 27.2 cm2/Vs.

Issues of amorphous oxide semiconductors (AOSs) thin-film transistors (TFTs) mainly focus on improving electrical performance and stability. Currently, the hump, the abnormal transfer characteristic, is also an essential factor of AOSs TFT. The hump phenomenon was observed for AOS-TFTs with a metal capping (MC) layer under various measurement conditions. The mobility in the MC TFT was improved from 14.8 cm2/Vs to 19.2 cm2/Vs compared to that of the conventional TFTs. The improved electrical characteristics in the MC structure are representative of the carrier injection effect and the change of the current path. This reason reveals that the MC structure has a hump phenomenon under the low drain to source voltage ( $V_{DS}$ ). The hump characteristic does not significantly affect the overall MC TFT characteristics (transfer characteristic, improved electrical characteristics through MC structure, etc.). In addition, it was confirmed that it exhibits very stable hump characteristics through repeated measurements and uniformity. It was found that two current paths are formed mainly due to carrier injection from the metal capping layer in the hump phenomenon observed at low $V_{DS}$ . These divided current paths can lead to two on-currents ( $I_{on}$ ) in the transfer curve. Many studies have recently been conducted to fabricate semiconductor devices with multi-values such as 0, 1, and 2. This divided current path could propose a simple method to achieve multi-values with an easy process.

Solution-processed In-Zn oxide (IZO) semiconductor thin-film transistors (TFTs) were fabricated with passivation layers of either poly(methyl methacrylate) (PMMA) or cyclic transparent optical polymer (CYTOP). According to the transfer curves obtained on the day of fabrication and after 200 days, the drain-source current of the IZO TFT without a passivation layer decreased by approximately 37 %. For the PMMA-passivated IZO TFT, it decreased by approximately 31 %. The current for the CYTOPpassivated IZO TFT showed significantly lower, only 7 % deterioration. Hence, the CYTOP-passivated IZO TFT exhibited improved electrical stability under long term ambient storage. This was attributed to the difference in the chemical composition of the two polymers, as CYTOP is a fluoropolymer, while PMMA is an ester group containing organic polymer. We show, passivation of the active layer with the proper organic film improves the stability of the high-performance solution-processed IZO TFTs.

A gate driver in array (GIA) design based on the amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) is developed for narrow border displays. In the design, each TFT in the gate driver circuits is divided into a certain number of smaller size devices, which can be placed in different subpixels. Therefore, the pixel aperture ratio loss is minimized, and uniform placement of the gate driver circuits over the pixel array area is able to be achieved. The proposed step-like repeating block structure further reduces the occupied area of the signal interconnects. A 12.4-inch fringe field switching (FFS) liquid crystal display (LCD) panel of ultra-narrow border (0.5 mm) is demonstrated with reliable operation based on this GIA design, proving its potential for practical applications.

The theory of oxygen vacancy related deep energy defects and valence band offset (VBO) between gate insulator and channel codetermining the threshold voltage shift $(\Delta {V}_{\mathbf {\mathrm {TH}}})$ of ZnO thin film transistor under negative gate bias and illumination stress (NBIS) is proposed and investigated systematically. Two kinds of ZnO thin film transistors are fabricated by atomic layer deposition with different gate oxide structures, a control sample with Al2O3 gate oxide and an improved sample with SiO2/Al2 ${\text{O}}_{3 }$ gate oxide structures. Among two kinds of devices, the device with SiO2/Al2 ${\text{O}}_{3 }$ gate oxide achieves a smaller $\mathbf {\mathrm {\Delta }}{V}_{\mathbf {\mathrm {TH}}}$ under the NBIS with SiO2 thin film acting as a holes-blocking layer, despite the existence of more defects than control device. The improvement in stability is attributed to large VBO up to 3.08 eV. Moreover, the device with SiO2/Al2 ${\text{O}}_{3 }$ gate oxide is evaluated on a 500-nit LCD back light to simulate the practical working environment in displays, which exhibits good stability of ${\mathbf {\Delta }{V}}_{\mathbf {\mathrm {TH}}}\,\,=\,\,-0.3$ V for 3600 seconds.

This letter presents a thin-film transistor architecture, in which a “trench” is introduced between the source and drain electrode to enhance current flow. The top-gate top-contact oxide Trench thin-film transistor has a superior on-current per width of $27.7~\mu \text{A}/ \mu \text{m}$ at a drain voltage of 4.1 V. It also has a good subthreshold swing of 0.122 V/dec and turn-on voltage of −0.4 V. This study explores the operating mechanism of the high-current-driving Trench oxide thin-film transistor. [ABSTRACT FROM AUTHOR]

We report a 38 $\mu \text{m}$ -pitch gate driver with three outputs using low-temperature poly-Si oxide (LTPO) thin-film transistors (TFTs) for ultra-high definition (UHD) display. A single stage of the proposed gate driver circuit consists of ten TFTs, six p-type low-temperature poly-Si (LTPS) and four n-type amorphous InGaZnO (a-IGZO) TFTs for three outputs. Three clock (CLK) signals are used for three outputs in one stage. The fabricated gate driver circuit, using the depletion mode a-IGZO TFTs with threshold voltage ($\text{V}_{{{\mathrm {TH}}}}$) of −3.5 V, successfully operates with a pulse width of $1~\mu \text{s}$. This can be used for 8k4k resolution display operated at refresh rate of 240 Hz. The power consumption can be as low as 9.4 mW at 4k2k ($3840\times2160$) resolution operated at 120 Hz. The proposed gate driver therefore can be utilized for UHD display with LTPO TFT backplane. [ABSTRACT FROM AUTHOR]

This study presents a comparative analysis of the performance of a p-type (Pentacene) organic thin-film transistor (OTFT) for temperature sensing using organic and inorganic dielectrics (low-k dielectric and high-k dielectrics) such as PVA, SiO2, and HfO2 in the saturation region of device operation. The device and the channel parameters such as mobility, threshold voltage, etc. are extracted using the conventional extraction approach at a temperature range of 293– 363 K. The simulation findings indicate how these characteristics change as a function of temperature, and hence could be employed in sensing applications. It is realized that the optimum performance is shown by the high-k dielectric (HfO2), where the mobility is $\sim \,\,4.25\times 10^{-3}$ cm2 /Vs, a low subthreshold slope of 59.6 mV/decade, a high ON/OFF ratio close to $9.4\times 10^{16}$ , low contact resistance of 1.1 $\text{G}{\Omega }$ and threshold voltage ($\text{V}_{{\mathrm {TH}}}$) decreases linearly (positive shift) with increasing temperature. The low value of $\text{V}_{{\mathrm {TH}}}$ ensures low operating voltage thus enabling the realization of a low power temperature sensor. It is shown that there is a 104 percentage change in the ON/OFF ratio which leads to the conclusion that the ON/OFF ratio can be a deciding factor in determining the optimum device parameter for sensing applications. Apart from this, the threshold voltage and the subthreshold slope (SS) are also equally important that affect the performance of the sensors. Notably, the temperature coefficient which denotes the change in device parameter per degree change in temperature is calculated for a more comprehensive study. It is observed that the temperature coefficient for drain current is $11.8\times 10^{-3}$ ng a large change in electrical characteristics when the temperature is altered by 1 kelvin. [ABSTRACT FROM AUTHOR]

Ultraviolet photodetectors (UVPDs) based on diode-connected In-Ga-ZnO (IGZO) thin-film transistors (TFTs), called field-effect diodes (FEDs), are presented. A patterned NiO capping layer (CL) deposited on the top surface of the IGZO channel forming a heterojunction (HJ) was employed to further improve UV detection performance. Experimental results show that FED-based UVPDs have advantages over traditional TFT-based UVPDs, achieving a minimum dark current without additional gate bias and a wider bias range for detection measurements. UVPDs based on the 30-nm-thick IGZO FED with NiO CL show a photoresponsivity and photosensitivity of up to 1376 A/W and $9.10\times10$ 7 A/A at 275 nm under ${V} _{D}$ = −1.5 V, which is about $25\times $ and $1480\times $ higher than the case without NiO CL. These improvements are due to the fact that the NiO CL/IGZO HJ reduces the effective channel thickness to suppress dark current and provide additional optically generated electrons in the channel and an additional negative threshold voltage shift to enhance the photocurrent. [ABSTRACT FROM AUTHOR]

A self-aligned fabrication process for top-gate amorphous zinc-tin oxide (a-ZTO) thin-film transistors (TFTs) is developed, in which the source/drain (S/D) doping is realized through depositing a thin aluminum (Al) film on S/D regions and performing a thermal annealing. Results indicate that a chemical oxidation-reduction reaction between Al and a-ZTO films takes place during the thermal annealing process, and shallow donors of oxygen vacancies and metal tin (Sn) interstitials are thus generated. The formed S/D regions have a high carrier concentration over $1 \times 10 ^{20}$ cm $^{-3}$ , low sheet resistance of 0.57 k $ {\Omega }$ /sq, and high thermal stability even in oxygen ambient. The fabricated a-ZTO TFTs exhibit excellent electrical performances, including a low channel-width-normalized S/D resistance of about $7.05~ {\Omega }$ cm, a high field-effect mobility of 15.7 cm2/Vs, a high on/off current ratio of over $10 ^{8}$ , and near-zero turn-on voltage. Moreover, good electrical stability with less than 0.2-V threshold voltage shift under ±30-V gate bias stresses is also achieved.

An accurate and efficient noise-based simulation technique for predicting the impact of device-parameter variability on the DC statistical behavior of integrated circuits is presented. The proposed method is validated on a source follower, a diode-load inverter and a current mirror based on organic thin-film transistors. Taking advantage of the standard noise analysis of a circuit, after translating the statistical variation of the electrical parameters of the transistors into equivalent-noise circuit components, the proposed technique yields results identical to those obtained from a Monte Carlo simulation, but in a significantly shorter amount of time.

We demonstrate the first wide bandgap oxide based negative capacitance transparent thin-film transistor (NC-TTFT) built on glass. The Mg0.03Zn0.97O (MZO) semiconductor served as the channel layer and ferroelectric Ni0.02Mg0.15Zn0.83O (NMZO) serves in the gate stack. The Al-doped ZnO (AZO) is employed as the transparent conductive oxide (TCO) for source and drain electrodes. The NC-TTFT on glass shows an average optical transmittance of 91 % in the visible spectrum. The subthreshold swing (SS) value is significantly reduced over the reference transparent thin-film transistor (TTFT) without a ferroelectric layer. The minimum SS value of the NC-TTFT reaches 17 mV/dec. With normally-off operation and high on/off current ratio of 107, this NC-TTFT on glass technology shows promising potential for wearable systems such as augmented reality (AR) smart glasses.

This article presents formulations for the voltage-in-current (VinC) latency insertion method (LIM) for thin-film transistors (TFTs). LIM is a fast circuit simulation algorithm that solves circuits in a leapfrog manner, without requiring intensive matrix operations present in SPICE-based simulators. This allows LIM to have a far superior scaling with respect to the size of the circuit resulting in significant time savings on large circuit networks. The VinC LIM formulation for the TFTs written in this article has the benefit of a better stability compared to the original LIM formulation which allows the use of larger time steps. The performance of the new algorithm is demonstrated through the simulation of numerical examples of large flat-panel display (FPD) circuits. It is seen that VinC LIM greatly outperforms basic LIM and commercial SPICE-based simulators, where the presented algorithm is able to simulate circuits with more than 10 million nodes or devices in a reasonable time, which is not viable in many modern day SPICE-based simulators.

Composed of computation units each containing a parallel, dual-gate (DG) thin-film transistor (TFT) and a memory capacitor addressed by an access TFT, a neuromorphic circuit implementing fundamental AND and OR logic functions is realized and characterized. The exceptionally low leakage current of a TFT built on indium-gallium-zinc oxide (IGZO) allows the capacitor to be used as a quasi-static memory element. Appropriate weight signals for the realization of the two logic functions are obtained using a gradient-descent training algorithm. The circuit can be configured to execute one of the two functions by the setting of the weight signals. [ABSTRACT FROM AUTHOR]

We report a novel emission gate driver using low- temperature poly-Si oxide (LTPO) thin-film transistors (TFTs). The proposed circuit consists of eight p-type low-temperature poly-Si (LTPS) and four n-type amorphous InGaZnO (a-IGZO) TFTs. The output pulse width is adjustable by changing the position of starting control signal which has constant pulse width without additional clock signals. The emission gate driver releases the output signals with various duty ratios. Excellent gate driving performance is achieved from the LTPO emission gate driver, although the a-IGZO TFTs have the threshold voltage of −5.5 V. In addition, the power consumption is as low as 5.98 mW in case of 80 $\boldsymbol {\mu }\text{s}$ pulse, 10 times of gate pulse, at refresh rate of 120 Hz with full high-definition ($1920\times1080$) for active-matrix organic light- emitting diode (AMOLED) display. [ABSTRACT FROM AUTHOR]

Oxide semiconductors have been considered one of the most promising candidates for flexible electronics applications owing to their low process temperatures and good reliability. However, the low mobility of p-type oxide semiconductors limits the performance of flexible oxide-TFT-based CMOS technology. In this study, p-type SnOx:Ni thin films were deposited by reactive rf magnetron co-sputtering, a technique compatible with the current industrial semiconductor manufacturing technology, from Sn and Ni targets. As the Ni-gun power increased, the distribution of Ni in the SnOx:Ni thin film changed from a more uniform dispersion to nanoclusters, resulting in the crystalline phase transition of SnOx:Ni from $\alpha $ -SnO (110)-dominant polycrystalline to amorphous and then to $\alpha $ -SnO (101)-dominant polycrystalline. A high-mobility inverted-staggered p-type SnOx:Ni TFT was then fabricated on a glass substrate with a maximum process temperature of 225°C, which is compatible with flexible polymeric substrates. The TFT fabricated at an optimal Ni-gun power of 42 W exhibited an impressive field-effect mobility of 11 cm2V−1s−1 and on current of $35.2 ~\mu \text{A}$ per channel width-to-length ratio; these values are comparable to those of a typical n-type oxide TFT. These results should contribute toward flexible oxide-TFT-based CMOS technology. [ABSTRACT FROM AUTHOR]

In this work, indium-tin-oxide (ITO) transistors with atomically thin channel thickness (${T}_{ch}$) of 2.1 nm realized by atomic layer deposition (ALD) are demonstrated. A maximum ON-state current of 970 mA/mm at ${V}_{DS}$ of 0.8 V and an ON/OFF ratio up to 107 are achieved in ITO transistor with In:Sn ratio of 9:1, channel length (${L}_{ch}$) of 60 nm, and dielectric equivalent oxide thickness (EOT) of 2.1 nm. Comparison between devices with different In:Sn ratios indicates a significant reduction of electron transport resulting from more Sn concentrations in ITO. The impact of back-end-of-line (BEOL) compatible low-temperature annealing is also investigated. An enhancement-mode operation with minimum subthreshold slope (SS) of 80 mV/dec and maximum field-effect mobility ($\mu _{FE}$) of 28 cm2/ $\text{V}\cdot \text{s}$ is achieved after O2 annealing. Besides, bias instability measurement shows the negative threshold voltage (${V}_{T}$) shift under both positive and negative gate bias stress due to donor-like interface states below the trap neutral level (TNL). The realization of large-area synthesis of atomically thin ITO films by ALD and decent electrical performance provide opportunities in future monolithic 3-D device integration with BEOL compatibility. [ABSTRACT FROM AUTHOR]

Device scaling of oxide-channel thin-film transistors (TFTs) toward sub-micrometer regime has been an urgent issue to realize higher-resolution displays and 3-D structured electronic devices. The channel-shortening effect is a serious problem in implementing the oxide TFTs with short channel lengths. In this work, the short-channel effects (SCEs) of the In-Ga-Zn-O (IGZO) TFTs were investigated with the variations in channel composition when the channel length was varied from $3~\mu \text{m}$ to 500 nm. Effective channel lengths were examined to decrease with increasing the In contents, in which the reduction of the effective channel length was estimated to be 240 and 720 nm when the In/Ga ratio increased 0.7 to 1.4. The drain bias-dependent roll-offs in turn-on voltages, which typically correspond to drain-induced barrier-lowering (DIBL), also showed significant channel composition dependence. When the In/Ga ratio within the channel increased from 0.2 to 1.4, the DIBL coefficients were estimated from 22 to 244 mV/V for the devices with a channel length of 1 $\mu \text{m}$. The channel composition-dependent variations in the effective channel length were suggested to result from the inter-diffusion and redox reactions at interfaces between the channel and electrode layers. Alternatively, the contact resistances were also examined to play major roles in determining the SCEs with scaling the devices, especially when the In contents decreased in the channel composition. Thus, properly controlling the channel composition can be concluded as such an important issue for compromising both technical strategies to reduce the channel resistance and to suppress the reduction of effective channel length. [ABSTRACT FROM AUTHOR]

In this work, we report the experimental demonstration of In2O3 3-D transistors coated on fin structures and integrated circuits by a back-end-of-line (BEOL) compatible atomic layer deposition (ALD) process. High-performance planar back-gate In2O3 transistors with high mobility of 113 cm2/ $\text{V}\cdot \text{s}$ and high maximum drain current (${I}_{\rm D}$) of 2.5 mA/ $\mu \text{m}$ are achieved by channel thickness engineering and postdeposition annealing. The high-performance ALD In2O3-based zero- ${V}_{\rm GS}$ -load inverter is demonstrated with a maximum voltage gain of 38 V/V and a minimum supply voltage (${V}_{\rm DD}$) down to 0.5 V. Top-gate indium oxide (In2O3) transistors by low-temperature ALD of both gate insulator and channel semiconductor are also demonstrated with ${I}_{\rm D}$ of $570~\mu \text{A}/\mu \text{m}$ and low subthreshold slope (SS) down to 84.6 mV/decade. ALD In2O3 3-D Fin transistors with the top-gate structure are then demonstrated, benefiting from the conformal deposition capability of ALD. These results suggest that ALD oxide semiconductors and devices have unique advantages and are promising toward BEOL-compatible monolithic 3-D integration for 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) severely degrade under AC gate bias stress and AC drain bias stress, whose transfer curves respectively undergo positive shifts of 6.3 and 14.2 V after a stress time of 3000 s with a stress amplitude of 20 V. In this study, annealing at 400 °C in O2 atmosphere is performed to effectively reduce the acceptor-like trap states in the a-IGZO channel and the electric field in the etching-stop layer under the extended drain electrode, which participate in dynamic and DC degradation mechanisms, respectively. Thus, a-IGZO TFTs exhibiting excellent stability without any shift of the transfer curve under the same AC gate bias stress and AC drain bias stress are experimentally demonstrated simultaneously. [ABSTRACT FROM AUTHOR]

We report a novel gate driver integrated by low-temperature poly-Si oxide (LTPO) thin-film transistors (TFTs). The proposed gate driver consists of four p-type low-temperature polycrystalline silicon (LTPS) TFTs and two n-type amorphous indium gallium zinc oxide (a-IGZO) TFTs. Dual-gate (DG) a-IGZO TFTs, having high drain currents and excellent reliability, are utilized. The fabricated gate driver operates with a pulse width of $1~\mu \text{s}$ corresponding to operating speed of 500 kHz at voltage swing of 15 V. Also, the proposed LTPO gate driver works well without malfunction with strong depletion mode a-IGZO TFTs having threshold voltage of −5.5 V. It is exhibited that the ripples, which appear when a-IGZO TFTs have negative threshold voltage, are perfectly removed by regulating two input DC signals. [ABSTRACT FROM AUTHOR]

In this letter, the carrier mobility of amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) was remarkably enhanced by the introduction of nitrogen and the formation of Zn3N2, in which the saturation field-effect mobility ($\mu _{\text {sat}}$) was 61.6 cm2/Vs. Annealing temperature plays a key role on the enhancement of carrier mobility. When the annealing temperature was increased to 400 °C, $\mu _{\text {sat}}$ was reduced to 4.1 cm2/Vs, which was proposed to be due to the formation of defective ZnxNy based on X-ray photoelectron spectroscopy results. In addition, the a-IGZO TFT with enhanced mobility did not exhibit persistent photoconductivity behavior. The high carrier mobility could expand the application of a-IGZO TFTs to functional circuits in active-matrix displays. [ABSTRACT FROM AUTHOR]

In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure. Both JL and IM TFTs can exhibit high on/off current ratio over 107 to demonstrate their performance. The JL TFT has much higher on-state current ~ 24 times than it of the IM TFT. And the IM-TFT has much lower SS ~ 0.104 V/decade and off-current ~ 0.04 times than them of the JL TFT. However, the fabrication of the top-devices (JL TFTs) would degrade the performance of underlying-devices (IM TFTs), resulting in the threshold voltage shift of the IM TFTs from 0.61 to 2.17 V, SS increase from 0.104 to 0.218 V/decade and on-state current degradation from 16 to 3 mA. In order to further understand the reasons, the IM TFT with top-device removal process is also fabricated, which exhibits a partial recovery in performance. The results indicate the presence and fabrication process of the top-device would lead to the defect generation in the underlying-device. The results provide a new consideration for monolithic 3D-IC manufacturing technology.

Low-frequency noise is a critical characteristic of transistors, but there are only a few experimental works on the noise in printed electronics. In this work, we characterize the low-frequency noise of inkjet-printed electrolyte-gated thin-film transistors (EGTs) with indium-oxide semiconductors. We confirm that the carrier number fluctuation with correlated mobility fluctuation is the dominating noise generation mechanism. Also, we present the benchmark analysis on the noise level of various thin-film technologies. Notably, the extracted value of trap density near the insulator-channel interface is high, indicating an inferior quality of solution-processed and inkjet-printed thin-films. However, because of electrolyte-gating, the large areal gate capacitance compensates the negative effect of the high trap density, effectively reducing the flat-band voltage noise. As a result, the normalized drain current noise is considerably lower than solution-processed transistors and comparable with sputtered inorganic transistors with dielectric gating. This renders the electrolyte-gating approach useful in reducing the noise for printed/solution-based transistors, suitable for low-noise applications. [ABSTRACT FROM AUTHOR]

In this article, we demonstrate atomic-layer-deposited (ALD) indium oxide (In2O3) transistors with a record high drain current of 2.2 A/mm at VDS of 0.7 V among oxide semiconductor transistors with the enhancement-mode operation. The impact of back-end-of-line (BEOL) compatible low-temperature annealing is systematically studied on these highly scaled In2O3 transistors with channel length (Lch) down to 40 nm, channel thickness (Tch) down to 1.2 nm, and equivalent oxide thickness (EOTs) of 2.1 nm, at annealing temperatures from 250 °C to 350 °C in N2, O2, and forming gas (FG, 96% N2/4% H2) environments. Annealing in all different environments is found to significantly improve the performance of ALD In2O3 transistors, resulting in enhancement-mode operation, high mobility, reduced bulk and interface trap density (Dit as low as 6.3 ×1011 cm−2 ⋅ eV−1), and nearly ideal subthreshold slope (SS) of 63.8 mV/dec. Remarkably, the ALD In2O3 devices are found to be stable in hydrogen environment, being less affected by the well-known hydrogen doping issue in indium–gallium–tin-oxide (IGZO). Therefore, low-temperature ALD In2O3 transistors are highly compatible with the hydrogen-rich environment in BEOL fabrication processes. [ABSTRACT FROM AUTHOR]

With development of high efficiency organic light emitting diodes (OLEDs), and high mobility polycrystalline silicon (poly-Si) thin-film transistors (TFTs), low power and high resolution active matrix OLED (AMOLED) displays are becoming popular for mobile applications. However, they suffer from poor control of lower gray levels, with the driving TFT being operated in the subthreshold regime. In this paper, with help of non-ideal drain-bias dependent electrical characteristics of poly-Si TFTs, operation of the driving TFT can be moved out from the subthreshold regime to allow better control of the gray levels. As a result, a dynamic voltage scaling (DVS) method is developed, and shown to be able to improve the luminous uniformity for better image quality, while effectively reducing the static power consumption.

Amorphous IGZO thin-film transistors (TFTs) in an etch stop layer (ESL) structure was processed on 2500 mm × 2200 mm size substrate. The fabricated devices exhibit enhancement mode characteristics, and excellent uniformity over large area. The presented good operational stabilities under both positive gate bias temperature stress (PBTS) and negative gate bias temperature stress (NBTS) tests can well meet the requirements for pixel switching. However, considering even threshold voltage shift under long term positive bias stress might affect proper operation of the gate driver on array (GOA), a design with a pulse gating scheme is proposed, consisting of 13 TFTs and 1 capacitor, to avoid long term continuous bias stressing of the TFT. With the proposed GOA design, a 32-inch QUHD (7680×4320) highresolution liquid crystal display (LCD) panel with a 7 mm wide bezel is achieved. The reliability of the GOA circuit is well proved through standard aging tests.

Etch-stopper-layer (ESL) structured amorphous InGaZnO thin-film transistors (a-IGZO TFTs) were fabricated in this article. Degradation behavior of the a-IGZO TFTs under hot-carrier stress and illumination (HCIS) was investigated. As HCIS time increases, the transfer curve in the saturation region shifts in the negative direction under the forward-operation mode, whereas it shifts in the positive direction under the reverse-operation mode. The HCIS-induced degradation behavior was attributed to charge trapping in the IGZO/ESL interface. To examine the degradation mechanism, the capacitance–voltage measurements were performed. After applying HCIS, it is found that the gate-to-drain capacitance curve shifts in the positive direction and the gate-to-source capacitance curve exhibits two-stage rises. Technology computer-aided design (TCAD) was used to simulate the electric field distribution during the stress, which also confirmed the proposed mechanism. [ABSTRACT FROM AUTHOR]

This work reports a method to reduce the process thermal budget in metal oxide (MO) thin-film transistors (TFTs). Using the thermal curing of a fluorinated polyimide planarization (PLN) layer as an efficient device activation process, this method eliminates the need for additional annealing steps before the existing PLN process in the fabrication. Bottom-gated TFTs with indium tin oxide (ITO)-stabilized ZnO channels were fabricated by this method and exhibited improved electrical characteristics over control devices made with a higher thermal budget. A steep subthreshold swing of 82.8 mV/decade and a high on-off ratio of ${1.3}\times {10}^{{10}}$ were achieved. This improvement can be attributed to the fluorine diffusion from the PLN layer to the MO channels during the curing step. This method is useful for the cost-effective production of active-matrix flat-panel display (AM-FPD) panels and the implementation of MO TFTs on flexible substrates. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate scaled back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by atomic layer deposition (ALD) with channel thickness (Tch) of 1.0-1.5 nm, channel length (Lch) down to 40 nm, and equivalent oxide thickness (EOT) of 2.1 nm, with record high drain current of 2.0 A/mm at VDS of 0.7 V among all oxide semiconductors. Enhancement-mode In2O3 transistors with ID over 1.0 A/mm at VDS of 1 V are also achieved by controlling the channel thickness down to 1.0 nm at atomic layer scale. Such high current density in a relatively low mobility amorphous oxide semiconductor is understood by the formation of high density 2D channel beyond $4\times 10^{13}$ /cm2 at HfO2/In2O3 oxide/oxide interface. [ABSTRACT FROM AUTHOR]

We report the effect of N2O post-fabrication annealing (PFA) on the electrical stability of dual gate, active split amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT). Optimized N2O PFA at 360 °C for 3 h results in threshold voltage (VTH) close to zero and an increase in the on-current almost 2 times than as-fabricated TFT. N2O annealed TFT exhibited robust VTH stability under positive bias temperature stress at 60 °C and negative bias illumination stress, exhibiting $\Delta \text{V}_{\text {TH}}$ of 0.1 V, and- 0.1 V, respectively, whereas as-fabricated TFT showed large $\Delta \text{V}_{\text {TH}}$ of ~ 10 V and −3 V. The X-ray photoelectron spectroscopy depth profile reveals the origin of such improvement as the increasing metal-oxide bonds and the reduction in oxygen vacancy / OH related defects. [ABSTRACT FROM AUTHOR]

Various reliability issues of low temperature polycrystalline silicon (LTPS) tunnel field-effect transistor (TFET) are comprehensively studied for the first time and compared with conventional LTPS thin-film transistor (TFT). For the positive and negative gate bias stress (P/NGBS) instability, the NGBS causes more serious electrical degradation for both LTPS-TFETs and TFTs because of the higher trap state generation after the NGBS. However, the local P/NGBS near the source-side and drain-side regions show completely different impacts on the LTPS-TFETs and TFTs. The results reveal that the source-side local P/NGBS dominates the entire P/NGBS effects of LTPS-TFETs, and the drain-side local P/NGBS effects have less impacts on the electrical behavior of LTPS-TFETs compared with the entire P/NGBS effects. For the LTPS-TFTs, the local P/NGBS effects show much less electrical degradation than the entire P/NGBS. The difference of local P/NGBS effects between LTPS-TFETs and TFTs is attributed to the different carrier transport mechanisms. In addition to the P/NGBS effects, the hot carrier stress (HCS) with different drain stress voltages is also studied in this work. The drain stress voltage would introduce the horizontal electric field near the junction and reduce the impact of the vertical electric field in the channel region. For the HCS of LTPS-TFETs, the increase of drain stress voltage only leads to the reduction of vertical electric field stress effect but no horizontal electric field stress effect, which is different from the results of LTPS-TFT. [ABSTRACT FROM AUTHOR]

Rectifiers are vital electronic circuits for signal and power conversion in various smart sensor applications. The ability to process low input voltage levels, for example, from vibrational energy harvesters is a major challenge with existing passive rectifiers in printed electronics, stemming mainly from the built-in potential of the diode’s p-n-junction. To address this problem, in this work, we design, fabricate, and characterize an inkjet-printed full-wave rectifier using diode-connected electrolyte-gated thin-film transistors (EGTs). Using both experimental and simulation approaches, we investigate how the rectifier can benefit from the near-zero threshold voltage of transistors, which can be enabled by proper channel geometry setting in EGT technology. The presented circuit can be operated at 1-V input voltage, featuring a remarkably small voltage loss of 140mV and a cutoff frequency of ~300 Hz. Below the cutoff frequency, more than 2.6-μW dc power is obtained over the load resistances ranging from 5 to 20 k Ω. Furthermore, experiments show that the circuit can work with an input amplitude down to 500mV. This feature makes the presented design highly suitable for a variety of energy-harvesting applications. [ABSTRACT FROM AUTHOR]

Three types of highly transparent inverter circuits, enhancement/depletion, pseudo-CMOS and feedback structures, are fabricated by using zinc-oxide thin film transistors (TFTs) with deuterium plasma immersion to adjust the threshold voltage of the depletion-mode TFTs. Their DC and AC performance are investigated and compared systematically. Especially, the feedback structure inverters demonstrate a maximum gain of −310V/V at ${V}_{DD} =10$ V, which is the highest DC gain ever to be reported for oxide TFTs. Furthermore, the frequency responses of these three inverter types are examined, showing a maximum AC gain of 210 V/V at a 10 mV amplitude input in the pseudo-CMOS inverters. These high-gain transparent inverters have great potential to be used as the common-source amplifiers in the measurement of photo-stimulated electroencephalogram signals. [ABSTRACT FROM AUTHOR]

This letter reports on a dual-mode wearable energy harvester that utilizes both piezoelectric and photoelectric effects. It integrates a piezoelectric transducer with a 3-D photosensitive dual-gate thin-film transistor (DGTFT) as a rectifier and a buffer. The energy conversion efficiency is enhanced by reducing the internal resistance of the 3-D photosensitive DGTFT upon light illumination. Such a dual-mode energy harvester is promising for wearable electronics. [ABSTRACT FROM AUTHOR]

We report an ambipolar phototransistor using the organic–inorganic hybrid perovskite, CH3NH3PbI3 [methylammonium lead iodide (MAPbI3)]. The high iconicity of MAPbI3 leads to intrinsic p-type and n-type self-doping, which enables simultaneous or selective hole and/or electron transport in a single device, depending on the bias conditions. Under white light illumination, both hole and electron current increase by four orders of magnitude and the dark characteristics recover completely and immediately after turning off the light source. In addition, the photosensitivity can be controlled by compositional ratio (MAI:PbI2) and the thickness of the MAPbI3 film. Moreover, the hole current shows higher responsivity and shorter response time (0.62 A/W and 100 ms) compared with electron current (0.20 A/W and 200 ms), resulting in respective photodetectivity values of 6.87 × 1015 and 1.33 × 1015 Jones. These photodetectivities are among the highest reported, making the phototransistors reported herein suitable for simple and cost-effective optoelectronics. [ABSTRACT FROM AUTHOR]

We report a highly sensitive thin-film transistor (TFT)-based temperature sensor with an ambient air-processed organic-inorganic hybrid perovskite, methylammonium lead iodide (MAPbI3), semiconductor. The threshold voltage of MAPbI3 TFTs shows a strong linear temperature dependency with a temperature coefficient of −200±10 mV/K – making them good temperature sensors. TFTs with an inorganic (PbI2)-rich or organic (MAI)-rich semiconductor exhibit less temperature sensitivity than those with the stoichiometric MAPbI3 film – thus attributing the high temperature sensitivity to trap states in the hybridized MAPbI3 perovskite structure. We show that ambipolar transport in MAPbI3 TFTs can be exploited to widen their temperature sensing window and demonstrate high sensing capability of a temperature sensor, consisting of a single MAPbI3 TFT in the diode configuration (with drain and gate shorted). [ABSTRACT FROM AUTHOR]

Here, we report a new strategy to fabricate high performance thin-film transistors (TFTs) by doping gallium (Ga) both in channel (In2O3) and dielectric (Al2O3) layers. The influence of Ga doping on the microstructure and surface morphology of In2O3 films, as well as the oxygen defects states and electrical properties of Al2O3 films have been systematically investigated. The results show Ga doping frustrates In2O3 crystallization and flattens film surface. As for Al2O3, Ga doping increase the dielectric constant, reflective index and decrease the leakage current density. Furthermore, metal oxide TFTs were developed when using In2O3:Ga as the channel and Al2O3:Ga as the dielectric layers. The devices show improved electrical performance and enhanced positive and negative bias stress stability than undoped devices. [ABSTRACT FROM AUTHOR]

While offering a range of practical benefits, the monolithic integration of low-temperature polysilicon (LTPS) and amorphous metal-oxide thin-film transistors presents several incompatibility issues regarding materials and processes. Presently addressed are two critical ones arising from the back-end processes of contact treatment and metallization. Both are resolved by employing a stacked-interconnect consisting of two conductor layers, with each layer forming the preferred contact electrodes for one of the two types of transistors. At the expense of a slight increase in process complexity, a narrow distribution of low specific contact resistance (∼ 10−5Ω ⋅ cm2) for both types of transistors was obtained, thus giving rise to more consistent transistor characteristics. Inverters consisting of complementary top-gate LTPS pull-up and bottom-gate indium-gallium-zinc oxide pull-down transistors were demonstrated, exhibiting a gain of 40 V/V and a rail-to-rail full swing. [ABSTRACT FROM AUTHOR]

Bottom-gate indium aluminum zinc oxide thin-film transistors (TFTs) are fabricated with a HfO2 dielectric layer using plasma enhanced atomic layer deposition (PEALD). The electrical properties and photoresponse are both affected by the method of post annealing. A device that is annealed at a temperature of less than 200°C has a better Ion/Ioff of $1.71\times 10^{{8}}$ and a lower subthreshold swing (S.S.) of only 0.21 V/dec. This demonstrates that proper annealing treatment increases the performance of the device. The photoresponse is also calculated. A TFT that is not annealed has a poor photoresponse and a lower rejection ratio. Annealing at a temperature of less than 200 °C gives a good photoresponse of 0.2 A/W and a high rejection ratio of $2.86\times 10^{{5}}$. An IAZO TFT with a HfO2 dielectric layer that is deposited using PEALD is applicable in UV sensing technology. [ABSTRACT FROM AUTHOR]

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with HfLaO as high-k gate dielectric have been fabricated, and p-type silicon wafers with resistivities of 0.001 ~ 0.002, 0.005, 0.02 ~ 0.021 and $5\sim 10\Omega \cdot $ cm are used as their gate electrodes. The carrier mobility of the samples show an increase with increasing gate acceptor concentration, indicating that the TFT performances are affected by the hole concentration in the gate electrode. The HfLaO gate dielectric is highly polarizable and so produces surface-optical phonons, which can scatter the electrons in the IGZO channel to reduce their mobility. Therefore, this work directly demonstrates that the holes in the gate electrode can have a screening effect to suppress this remote phonon scattering of the gate dielectric on the channel carriers, just like the electrons in the metal gate, ITO gate and n-silicon gate of field-effect transistors. [ABSTRACT FROM AUTHOR]

In this letter, high-performance thin-film transistors (TFTs), with indium oxide (In2O3) as front channel layer, high permittivity ZrO2 as dielectric layer, and aluminum oxide (Al2O3) as passivation layers were integrated by a fully solution process. It is found that the incorporation of Al2O3 passivation layer gives rise to a sharp decrease in the off current (Ioff) and a corresponding increase in the on/off current ratio ($\text{I}_{\text {on}}$ /Ioff) of the TFTs, compared to that without Al2O3 passivation. Furthermore, the thickness effect of the passivation layer on the performance of In2O3 /ZrO2 TFTs has been investigated systematically. The In2O3 /ZrO2 TFTs with optimized Al2O3 passivation layers can be operated at 3 V with high performance, including a high field-effect mobility of 21.22 cm2 /V s, a large $\text{I}_{\text {on}}$ /I off of 107 and a negligible hysteresis (~0V). This work demonstrates an effective strategy for the construction of high performance TFTs by incorporating the passivation layer. [ABSTRACT FROM AUTHOR]

We used thin-film transistors (TFTs) to understand the effect of precursor composition on ion migration in the hybrid perovskite CH3NH3PbI3(MAPbI3). For all the precursor compositions we investigated (i.e. MAI/PbI2 ratios of 0.5, 0.8, 1.0, and 1.2), the TFTs exhibited anomalous hysteresis in their current-voltage (I-V) characteristics, indicating mixed ionic-electronic conduction. The hysteresis in the TFTs with MAI/PbI2 = 0.5 was the largest, followed by that of the TFTs with ratios of 1.2, 1.0, and 0.8. Although residual PbI2 was the source of hysteresis in the PbI2-rich TFTs (MAI/PbI2 = 0.5), we conclude that it may enhance electronic conduction and minimize ion migration when present in small amounts (as in the case of MAI/PbI2 = 0.8). Ion vacancy defects in grain boundaries are pathways for ion migration and the PbI2 residues passivate these defects, there by minimizing the vacancy-mediated migration of ions in the MAPbI3. [ABSTRACT FROM AUTHOR]

This letter proposes a high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO2 stack for thin-film transistors (TFTs), which contains a layer of SiH4-sourced PECVD SiO2 (SiH4-SiO2) with a layer of tetraethyl-orthosilicate (TEOS)-sourced PECVD SiO2 (TEOS-SiO2) underneath. The issues of high hydrogen content in the SiH4-SiO2 and rich hydroxyl groups in the TEOS-SiO2 were found to be well addressed by capping the TEOS-SiO2 with SiH4-SiO2. Moreover, the electrical properties of the SiO2 stacks were shown to be strengthened in comparison with their single-layer counterparts. This is owing to the mutual interactions between hydrogen groups in the SiH4-SiO2 and hydroxyl groups in the TEOS-SiO2. Top-gated indium–tin-oxide-stabilized ZnO TFTs with stacked gate insulators (GIs) were demonstrated after the optimizations of the GI layer thickness and deposition order and were shown to be free of hysteresis with a high ON–OFF ratio of over 1010 and a sharp subthreshold swing of 96.9 mV/decade. The combination of TEOS-SiO2 and SiH4-SiO2 initiates an economical strategy to achieve reliable GIs for high-performance top-gated metal-oxide TFTs. [ABSTRACT FROM AUTHOR]

Two bottom-gate indium aluminum zinc oxide thin-film transistors (TFTs) were fabricated with different dielectric layers. The TFT with Al2O3 deposited through atomic layer deposition (ALD) had higher field mobility of 0.48 cm $^{\mathbf {2}}/\text{V}\cdot \text{s}$ , Ion/Ioff of $9.7{}\boldsymbol {\times }{} 10^{\mathbf {7}}$ , and lower subthreshold swing of 0.3 V/dec. The hysteresis of the two devices showed that the device with Al2O3 dielectric layer had a lower threshold voltage shift (−0.065 V) compared with that of the device with the SiO2 dielectric layer (−0.352 V). These results revealed that the device with Al2O3 dielectric layer had fewer interface traps between the active layer and dielectric layer than the device with the SiO2 dielectric layer deposited through plasma-enhanced chemical vapor deposition. Because of the improvement of interface traps, the device with Al2O3 dielectric layer had high responsivity (6.18 A/W) and rejection ratio ($1.74{}\boldsymbol {\times }{} 10^{\mathbf {3}}$); this device has high potential for use in ultraviolet sensing applications. [ABSTRACT FROM AUTHOR]

Self-aligned top-gate (SATG) amorphous zinc tin oxide thin-film transistors (a-ZTO TFTs) are fabricated for the first time. Ar plasma treatment forms the self-aligned source/drain (S/D) region and reduces the sheet resistance of the a-ZTO S/D region from a very high value over the measurable limit to around 2.5 $\text{k}\Omega $ /□. The annealing temperature of the a-ZTO film has a strong impact on the electrical performances of the fabricated TFTs. The N2O plasma treatment prior to gate insulator deposition remarkably enhances the TFT performances. The fabricated a-ZTO TFTs present a field-effect mobility of 12.1 ± 0.27 cm $^{\textbf {2}}/\textsf {V}\cdot \textsf {s}$ , a subthreshold swing of 0.3 ± 0.03 V/decade, and good electrical stress stability under both positive and negative biases. A low-cost SATG a-ZTO TFT technology is thus well demonstrated. [ABSTRACT FROM AUTHOR]

Transparent polycrystalline p-channel copper bromide (CuBr) thin-film transistors (TFTs) are fabricated using a simple one-step spin coating at room temperature. Optimized CuBr TFTs operate in depletion mode with an on-voltage of 35 V and exhibit a hole mobility of 0.15 cm $^{2}\,\,\text{V}^{-1}\,\,\text{s}^{-1}$ , high ON/OFF current ratio ${\sim }10^{4}$ and cycling bias sweep/air stabilities. The performance is superior to that of most solution-processed p-type oxide TFTs, highlighting CuBr as a promising p-type candidate for next-generation printable transparent electronics. [ABSTRACT FROM AUTHOR]