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In this article, we propose a probabilistic machine learning framework for extrapolating the frequency response of distributed physical circuits. For the structures where there is hidden dependency between higher and lower frequency features, we propose a method to extrapolate the response while providing confidence intervals harnessing Bayesian recurrent neural networks (RNN) thereby avoiding extensive simulations and saving computational time. To address complex-valued impedance, Hilbert transform is used to relate the real and imaginary parts where a Hilbert-based RNN architecture is proposed called Hilbert Net to extrapolate the frequency response. We apply the technique to four applications: 1) A simple microstrip transmission line circuit for proof of concept, 2) coupled waveguide filter operating in D-band comparing with measured results, 3) fifth-order interdigital bandpass filter for 28 GHz band, and 4) complex stack-up power delivery network (PDN) having a sharply changing response to test the framework limits. Results show that our architecture performs accurate extrapolation with a normalized mean square error of 0.008 squared with 95% confidence for a typical PDN. Using probabilistic networks, we achieve a tight confidence bound on our results. Furthermore, the reliability of Hilbert Net is assessed as to how far the response can be extrapolated. [ABSTRACT FROM AUTHOR]

In this article, we present an effective methodology for co-design, co-analysis, and the system-level optimization of chiplet/interposer power delivery network (PDN) in 2.5-D integrated chip (IC) designs. In our methodology, we first generate a commercial-grade heterogeneous 2.5-D IC designs including full signal routing and power delivery. We then perform our PDN co-analysis in frequency and time domains on the entire PDN to evaluate various mechanisms added to our PDN designs. Based on our co-analysis results, we perform the system-level optimization on both interposer and chiplet PDNs with the stable performance of power delivery. Finally, we perform power, performance, and area (PPA) analysis and power integrity (PI) on our 2.5-D designs and discuss tradeoffs in chiplet and interposer levels due to PDN optimization. Our experiments show 27.17% improvement in the overall IR-drop in the optimized 2.5-D IC design by increasing the interposer PDN occupancy by 5.52% and inserting the additional PDN grids in chiplet designs. However, we also observe tradeoffs in terms of PPA and PI. By PDN optimization, the optimized design has an 11.6% increase of the total power, while the area of 2.5-D design remains the same. Moreover, from the perspective of PI, the tradeoffs are shown by 0.6% reduction of power efficiency, 32.6% higher output ripple, and 31.5% higher initial ringing because of an inductive behavior of interposer PDN in the optimized design. [ABSTRACT FROM AUTHOR]

The 2-D CMOS process technology scaling may have reached its pinnacle, yet it is not feasible to manufacture all computing elements at lower technological nodes. This has opened a new branch of chip designing that allows chiplets on different technological nodes to be integrated into a single package using interposers, the passive interconnection mediums. However, establishing a high-frequency communication over an entirely passive layer is one of the significant design challenges of 2.5-D systems. In this article, we present a robust clocking architecture for a 2.5-D system consisting of 64 processor cores. This clocking scheme consists of two major components, namely, interposer clocking and on-chiplet clocking. The interposer clocking consists of clocks used to achieve global synchronicity and clocks for interchiplet communication established using the AIB protocol. We synthesized these clocking components using commercial EDA tools and analyzed them using standard tools, on-chip, and package models. We also compare these results against a 2-D design of the same benchmark and another 2.5-D clocking architecture. Our experiments show that the absolute clock power is up to 16% less, and the ratio of clock power to system power is up to 4% less in the 2.5-D design than its 2-D counterpart. [ABSTRACT FROM AUTHOR]

A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off-the-shelf intellectual properties (IPs), allows reuse of them, and enables heterogeneous integration of blocks in different technologies. In this article, we present a highly integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5-D designs. Our target design is 64-core architecture based on Reduced Instruction Set Computer (RISC)-V processor. We first chipletize each IP by adding logical protocol translators and physical interface modules. We convert a given register transfer level (RTL) for 64-core processor into chiplets, which are enhanced with our centralized network-on-chip. Next, we use our tool to obtain physical layouts, which is subsequently used to synthesize chip-to-chip I/O drivers and these chiplets are placed/routed on a silicon interposer. Our package models are used to calculate power, performance, and area (PPA) and reliability of 2.5-D design. Our design space exploration (DSE) study shows that 2.5-D integration incurs $1.29\times $ power and $2.19\times $ area overheads compared with 2-D counterpart. Moreover, we perform DSE studies for power delivery scheme and interposer technology to investigate the tradeoffs in 2.5-D integrated chip (IC) designs. [ABSTRACT FROM AUTHOR]

Neural networks (NNs) are widely used to create parametric models of S-parameters for various components in electronic systems. The focus of deriving these models has so far been numerical error reduction between the NN-generated S-parameters and the data source. However, this is not sufficient when creating such NNs since it does not guarantee predicted S-parameters to be physically consistent, i.e., passive and causal, which restricts their use cases. This article, therefore, proposes a causality enforcement layer (CEL) and passivity enforcement layer (PEL) that can be used in NNs, which ensures that NN-predicted S-parameters are of a passive and causal system. To achieve this, we utilize Kramers–Kronig relations and singular value properties of S-parameters during the training stage with the purpose of learning a physically consistent representation. This enables end-to-end training where no postprocessing is required to ensure physical consistency. We demonstrate the effectiveness of the presented approach for three different design applications, where the goal is to predict S-parameters from dc to 100 GHz. The results show that when NNs are trained using CEL and PEL, the predicted S-parameters are characterized as 100.0% causal and passive while having the same level of accuracy as NNs that solely focus on error minimization. [ABSTRACT FROM AUTHOR]

In this article, we cover the fundamentals of neural networks and Bayesian learning with a focus on signal and power integrity problems arising in packaging. Rather than only focus on mathematical formulations, we explain the important concepts and the intuition behind them, thereby demystifying the use of machine learning for these problems. We also share some of the recent developments in this area along with future research directions in the context of packaging. Links to open-source downloadable software for some of the methods discussed are also provided. [ABSTRACT FROM AUTHOR]

System-in-package (SiP) integration of multiple dies in a single package can achieve much higher performance than onboard integration of integrated circuits (ICs) while reducing the design cost/effort compared to a large system on chips (SoCs). However, a major challenge in the design of SiPs with many dies is automated design and insertion of input/output (I/O) cells to minimize energy and delay of the wire traces. This article presents an automated cell library generation flow for all-digital I/O circuits for SiP integration. Given parameterized models of SiP wire traces, our method automatically designs, optimizes, and generates layouts of I/O cells for delay/energy minimization. The proposed flow is demonstrated on interposer-based SiP integration considering 28-nm CMOS technology and 65-nm BEOL technology. Given a multidie SiP design and associated interposer wire traces, this article demonstrates that automated I/O library cell generation can reduce the maximum die-to-die communication delay or energy. We demonstrate the proposed flow for various interposer parameters and SiP designs to show the feasibility of chip-interposer codesign. [ABSTRACT FROM AUTHOR]

One of the more intriguing applications of wireless power transfer is power delivery for low-power Internet of Things (IoT) devices. By utilizing RF near-field coupling (NFC), an improved combination of small receiver coil area and system efficiency can be achieved, as is ideal for wireless charging for low-power IoT platforms. However, utilizing high efficiency RF NFC comes with a cost—various electromagnetic effects can lead to detuning of the resonant frequency if not properly modeled. In addition, integrating power regulation with high frequency ac–dc conversion can create large ripple voltage supply to a power distribution unit (PDU). This paper investigates the system level issues that arise in efficient, regulated RF NFC systems for milliwatt-scale output power. A method for modeling the various electromagnetic, frequency detuning effects is presented, as well as a selection process for the circuit component values in the design. Furthermore, a reverse power distribution network is designed to integrate the rectifier with a PDU, introducing a target impedance and phase considerations for an RF rectifier. The modeling and integration solutions are experimentally verified through two different RF NFC systems. The systems have measured peak efficiency of 68.4% at 3.3 V output and 58.6% for 1 V output with less than 100 mm $^2$ receiver coil area, demonstrating a unique combination of small coil area and high efficiency compared to other NFC systems to better support low-power IoT devices. [ABSTRACT FROM AUTHOR]

Efficient global optimization of microwave systems is a very challenging task that emerges in importance for rapid design closure and discovery of novel structures. As the operating frequency increases, additional difficulties in design optimization occur due to increased nonlinearity, creating a high-dimensional nonconvex response surface. Bayesian optimization (BO) is a promising solution to solve such problems. However, BO-based methods suffer from the curse of dimensionality, where the number of simulations required for convergence increases exponentially with the number of parameters. In this paper, we address this problem and propose a new BO-based high-dimensional global optimization method titled, Bayesian Optimization with Deep Partioning Tree (DPT-BO). DPT-BO leverages a novel DPT that allows for rapid coverage of high-dimensional sample spaces and utilizes an additive Gaussian process (ADD-GP) with a fully additive decomposition, making it more suitable for high-frequency design optimization. We apply DPT-BO to different optimization test functions along with three high-frequency design applications, namely, maximizing signal integrity in high-speed channels, minimizing losses of substrate integrated waveguides with air cavity, and maximizing efficiency of wireless power transfer systems. The results show that DPT-BO finds control parameters that provide better performance in less CPU time compared to other techniques. [ABSTRACT FROM AUTHOR]

Wireless power transfer (WPT) is an ideal power delivery solution for many light-load applications, such as for the Internet of Things. A regulated solution for WPT may utilize a power distribution unit (PDU). Previous works have designed planar inductors for integration with switched-inductor buck regulators, but these inductors will not be as efficient for light-load applications. This paper reevaluates the inductor loss for light-load applications by taking into account the frequency spectrum of the inductor current. Using this revised analysis, a planar inductor with screen printed NiZn ferrite epoxy composite magnetic core is designed for an RF near-field coupling system with 1–10-mW load power. In measurement with a 6-MHz buck converter, the PDU with designed inductor demonstrated up to 3% improved efficiency compared to surface-mount technology inductor in the pulse-frequency modulation mode and pulsewidth modulation mode. The designed embedded inductor was subsequently demonstrated in an integrated, compact RF near-field coupling system with peak 43% system efficiency. [ABSTRACT FROM AUTHOR]

Increasing levels of system integration pose difficulties in meeting design specifications for high-performance systems. Oftentimes increased complexity, nonlinearity, and multiple tradeoffs need to be handled simultaneously during the design cycle. Since components in such systems are highly correlated with each other, codesign and co-optimization of the complete system are required. Machine learning (ML) provides opportunities for analyzing such systems with multiple control parameters, where techniques based on Bayesian optimization (BO) can be used to meet or exceed design specifications. In this paper, we propose a new BO-based global optimization algorithm titled Two-Stage BO (TSBO). TSBO can be applied to black box optimization problems where the computational time can be reduced through a reduction in the number of simulations required. Empirical analysis on a set of popular challenge functions with several local extrema and dimensions shows TSBO to have a faster convergence rate as compared with other optimization methods. In this paper, TSBO has been applied for clock skew minimization in 3-D integrated circuits and multiobjective co-optimization for maximizing efficiency in integrated voltage regulators. The results show that TSBO is between $2\times $ - $4\times $ faster as compared with previously published BO algorithms and other non-ML-based techniques. [ABSTRACT FROM AUTHOR]