403 results on '"Tsai, C"'
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2. Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing
3. Effects of Temperature and Humidity on The Surface and Mechanical Properties of Beta-chitin/PCL Nanofibers Prepared by Electrospinning
4. 2.2 A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET
5. The Effect of Humidity on the Morphological Evolution of β-Chitin Prepared by Electrospinning
6. Wideband Self-decoupled Dual Antennas for 5G MIMO Operation in Smartphone
7. Next-Generation Design and Technology Co-optimization (DTCO) of System on Integrated Chip (SoIC) for Mobile and HPC Applications
8. First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)
9. High Transparent Hydrophilic Photocatalytic Thin Film on Glass using Rapid Plasma Modification
10. Low Temperature SoIC™ Bonding and Stacking Technology for 12/16-Hi High Bandwidth Memory (HBM)
11. SoIC for Low-Temperature, Multi-Layer 3D Memory Integration
12. The Seventh Visual Object Tracking VOT2019 Challenge Results
13. On Fusing Multiple Instance Selection Results
14. Fabrication and Characterization of Millimeter Wave 3D InFO Dipole Antenna Array Integrated with CMOS Front-end Circuits
15. Low Temperature SoIC Bonding and Stacking Technology for 12-/16-Hi High Bandwidth Memory (HBM).
16. Warpage Analysis of Fan-Out Panel-Level Packaging Using Equivalent CTE.
17. Advanced patterning approaches for Cu/Low-k interconnects
18. Geometric variation: A novel approach to examine the surface roughness and the line roughness effects in trigate FinFETs
19. Study of Surface Character of Micrometer-Scale Dipole-Exchange Spin Waves in an Yttrium Iron Garnet Film.
20. Ultra-low-resistance 3D InFO inductors for integrated voltage regulator applications
21. Transistor reliability characterization and comparisons for a 14 nm tri-gate technology optimized for System-on-Chip and foundry platforms
22. Optimization of fin profile and implant in bulk FinFET technology
23. 3D printing of low melting temperature alloys by fused deposition modeling
24. AlGaN/GaN MIS-HFET with improvement in high temperature gate bias stress-induced reliability
25. Improved trap-related characteristics on SiNx/AlGaN/GaN MISHEMTs with surface treatment
26. The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown
27. Magnetic thin-film inductors for monolithic integration with CMOS
28. Applying Social Marketing Theory to develop retargeting and social networking advertising website
29. A next generation CMOS-compatible GaN-on-Si transistors for high efficiency energy systems
30. Generalized aberration reduction of a concave grating for hyperspectral sensing
31. Waste electronics and electrical equipment disassembly and recycling using Petri net analysis
32. A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products
33. The RTN measurement technique on leakage path finding in advanced high-k metal gate CMOS devices
34. A flexible top metal structure to improve ultra low-k reliability
35. Acceleration of large-scale multi-physics simulation for biomedical EMC with manycore architecture based computing
36. Effect of underlayer on thickness dependent magnetic properties of Ni-Fe films
37. The understanding of the bulk trigate MOSFET's reliability through the manipulation of RTN traps
38. Ultra-low-power switching and complementary resistive switching RRAM by single-stack metal-oxide dielectric
39. New Observations on the Uniaxial and Biaxial Strain-Induced Hot Carrier and NBTI Reliabilities for 65nm Node CMOS Devices and Beyond.
40. The understanding of multi-level RTN in trigate MOSFETs through the 2D profiling of traps and its impact on SRAM performance: A new failure mechanism found
41. The understanding of the trap induced variation in bulk tri-gate devices by a novel random trap profiling (RTP) technique
42. The impact of the carrier transport on the random dopant induced drain current variation in the saturation regime of advanced strained-silicon CMOS devices
43. New criteria for the RDF induced drain current variation considering strain and transport effects in strain-silicon CMOS devices
44. Characteristics of HfZrOx gate stack engineering for reliability improvement on 28nm HK/MG CMOS technology
45. Design of wireless transcutaneous energy transmission system for totally artificial hearts.
46. Study on solid phase epitaxy formed embedded SiC by tilted cluster carbon ion implantation
47. New observations on the physical mechanism of Vth-variation in nanoscale CMOS devices after long term stress
48. Experimental determination of the transport parameters in high performance Dopant-Segregated Schottky-barrier MOSFETs
49. Colorless WRC-FPLDs Subject to Gain-Saturated RSOA Feedback for WDM-PONs.
50. The investigation of the stress-induced traps and its correlation to PBTI in high-kdielectrics nMOSFETs by the RTN measurement technique
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