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Shannon-Nyquist sampling theorem is the most fundamental and well known for transforming a continuoustime band-limited signal into its discrete-time form. Over the years, many other methods have been developed for the same. The sampling frequency i.e. the number of samples taken per second, is one of the important characteristics of the sampling process. Since high sampling frequency is very tedious to achieve in the practical world, one desire to have a sampling frequency as low as possible. This paper investigates the classical Sub-Nyquist sampling methods named as Demodulation, Undersampling and Periodically Non-uniform Sampling which reduces the sampling frequency below the Nyquist rate, assuming a multiband or bandpass signal with known frequency support. It will present a comparative study of these methods in terms of the sampling frequency with respect to both the Nyquist rate and the minimal sampling frequency possible, additional hardware circuitry needed and their suitability to multi-band inputs.

The prime motivation to use single Acoustic Vector Sensor for measuring acoustic intensity is lying in its compact size and the unambiguous two-dimensional direction of arrival estimation which is insensitive to the range, frequency and bandwidth of the impinging acoustic signal sources. While, the major limitation of its use for direction of arrival estimation stands with its limited degree of freedom leading to identification of the maximum two sources using conventional direction of arrival estimation methods. This paper proposes a compressive sensing based method utilising the fourth-order circular cumulants for two-dimensional direction of arrival estimation of multiple non-Gaussian signals. By using the proposed method, a single acoustic vector sensor be able to estimate two-dimensional direction of arrival of up to seven non-Gaussian statistical independent source signals corrupted by Gaussian noise but maximum four if all the sources lying in a single plane. Compared to existing fourth-order cumulants based methods, the proposed algorithm offers improved direction of arrival estimation performance such as higher spatial resolution, improved estimation accuracy and required lower signal to noise ratio and lesser number of snapshots to operate.

In this paper, the wrench-feasible printable workspace is analyzed for a planar redundant cable-driven 3D printer. This workspace has a characteristic feature of maintaining cable tension within the prescribed positive tension bounds while avoiding interference of lower cables with the object being printed for all the poses in the workspace. Furthermore, the effect of various geometric parameters on the workspace of the robot is studied. Finally, the miniaturization of a cable-driven 3D printer is achieved for a specified workspace by optimizing geometric parameters of the robot using the genetic algorithm.

This paper investigates the performance of various multiple input multiple output (MIMO) space-time coded systems. These systems are simulated under Rayleigh fading environment and their performance in terms of bit error rate (BER), diversity gain, data-rate, type of transmitted signal constellations and detection complexity is evaluated.

Miniaturization of mobile electronics and consumer devices has resulted in a three dimensional (3D) scaling trend for Wafer Level Chip Scale Packaging (WLCSP) technology. Horizontal scaling and the impact on device reliability have been described in detail in many previous publications. Horizontal scaling typically implies reduction in the I/O pitch leading to a smaller die size. The device reliability measured with respect to temperature-cycling tests and drop tests, improves as the I/O pitch reduces. Scaling rules have been developed for horizontal scaling. In this paper, we discuss the vertical scaling of WLCSP technology that does not follow conventional scaling rules. Aggressive scaling is implemented in the vertical dimension to arrive at a low form factor package technology. Such a packaging technology is extremely useful in space constrained, ultra-thin, consumer electronics products. We discuss the fabrication technology and then present the reliability results. A simple RC filter circuit is used as a test vehicle to compare the performance and reliability of the new LP-CSP process with the conventional CSP process.

We present a silicon technology that allows integration of precision passive components such as high density 3D-capacitors, resistors, and inductors with various diodes and zener devices. We couple this hyper-integration of passives in silicon with WLCSP packaging to design compact, high performance devices suitable for space constrained wireless and personal electronics applications. We demonstrate the application of this technology for designing a protection/filter IC for cellular microphone. The IC provides audio and RF filtering along with ESD protection compliant with IEC61000-4-2 specifications. All necessary components including the biasing network, high density capacitors (30 nF/mm2), diodes, and resistors are included on the chip. Packaged as a 1.2 mmtimes1.2 mm WLCSP device, and with all the integrated passive components, a high level of miniaturization is achieved.

The paper describes a modular 0.5 /spl mu/m, n+/p+ poly, Ti-salicided, double poly, triple metal technology combining high performance digital logic, precision analog components and non-volatile memory. The non-volatile memory is a simple, split-gate flash EEPROM which consumes little power during program, erase and read operations. Because of the low power/low voltage operation of individual devices, the overall technology is ideally suited for applications in high speed communication, computing and battery powered portable systems. >