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Wafer-level direct bonding technology is a key process for the production of backside illuminated (BSI) CMOS image sensor (CIS). Usually, constant-depth mode scanning acoustic microscope (C-SAM) 300mm wafer images are acquired and defect size distribution is provided to monitor defects that degrade bonding yield. This acquisition technique is used as it is nondestructive and is able to capture the full wafer. Current solutions are not providing information detailed enough to identify the root cause of this degradation. A consequence is that most measurements and classification is currently done manually which take time and have reproducibility issues. In this paper, we propose a rule-based method for the classification of the defects and automatic segmentation of the defects to extract precise measurements depending on the type of defect. The classes of defects are precisely defined based on their origin in the process. All these information will allow to reduce the time to analyze the images and improve the precision and consistency of the analysis. These results will allow to identify more precisely the defects thus the causes of yield degradation during bonding process. [ABSTRACT FROM AUTHOR]

This article introduces a new triaxial magnetic field gradiometer to detect, locate, and map underground metallic utilities, such as a thin wires, railroad tracks, and pipes. The system couples a primary electric field along target’s elongation to maximize excited linear electric (i.e., non-solenoidal) currents and uses magnetic field induction sensing (i.e., Faradays induction law) to measure secondary magnetic fields. First, theoretical and numerical studies are presented for the broadband electromagnetic response from long thin wires buried in a conducting soil at varying depths. Second, numerical calculations are validated against experimental data. Favorable comparisons between model and measured data are illustrated for wires subjected to both plane wave excitation, originating from a 1.4-MHz amplitude modulation (AM) station as well as local excitation. Third, forward and inverse electromagnetic models are applied to electromagnetic gradiometer (EMG) field data to extract the wire’s burial depths from different survey track data, showing good agreement for wire depths from 0 to ~6 m. Finally, multiwire location and orientation are extracted from the triaxial vector gradiometer dataset. These results illustrate the applicability of linear current sensing for detecting, locating, and mapping deep underground metallic infrastructures, such as wires, railroad tracks, and pipes. [ABSTRACT FROM AUTHOR]

This paper presents the space charge impact on the inception and propagation of electrical trees in cross-linked polyethylene (XLPE) insulation via simulations and experimentation. A 3D finite element analysis (FEA)-based modeling is proposed to simulate electrical trees via a needle embedded on the XLPE insulation. The proposed FEA model demonstrates the influence of the space charge magnitude and polarity on the initiation of partial discharges (PD). Then the critical parameters at the tip of an 8 µm. tree are to be examined. Experimentation is necessary to verify the simulation results acquired and study the mechanism of electrical trees at the inception and propagation stage. Therefore, in the experiment, a needle with a curvature radius of 5 µm. is embedded in the XLPE as a method of simulating defects, such as protrusions, voids, or cracks found in cable insulation. The power source supplies several high AC voltages on the 20 kV (rated voltage) cable under test for observing the inception and propagation behavior of the electrical trees. Phase-resolved partial discharge (PRPD) patterns are extracted at the inception and propagation stages of the electrical tree to determine the severity of the PDs occurring. A relationship is obtained for the PD magnitude with respect to the applied AC voltage while considering the positive and negative polarities of the PDs. This relationship then allows for the acquisition of the maximum electric field-tree length characteristics. The goal of the simulation of electrical trees is to provide the reader with a better understanding about the effect of space charge magnitude and polarity to comprehend the behavior of the treeing inception and propagation mechanisms. The injection and extraction of space charges is a complex phenomenon that requires further visualization through simulations. Therefore, the results of both the simulation and experiment are compared with the aim of establishing a clear relationship between space charge distribution and tree initiation. [ABSTRACT FROM AUTHOR]

This study investigates the relationship between void size and insulation lifetime due to partial discharges (PDs) in internal voids. Experimental results clearly show that the larger the void size, the shorter the insulation lifetime, which decreases the lifetime n-value index of the voltage-time characteristics. The results also show a clear relationship between the insulation lifetime of a solid insulator having void defects and the PD energy generated in the void, which is related to the cumulative PD energy density per cycle. Therefore, we propose estimating the insulation lifetime of an insulator with voids by calculating the cumulative PD energy density per cycle. [ABSTRACT FROM AUTHOR]

This paper reports results of a study on copper voids seen in a back end of line (BEOL) module. The experiment was designed to study the effect of multiple parameters that can influence the occurrence of voids and their process margins. This work also reports the effect of changes in copper seed thickness on the product’s lifetime and reliability. [ABSTRACT FROM AUTHOR]

High-power light-emitting diode (LED) chip-scale packages (CSPs) prepared by the flip-chip technology have become one of the most promising light sources. The die attach solder layer always plays an important role in heat dissipation, mechanical support, and electronic conductivity. Among different types of solder materials, Sn-3.0Ag-0.5Cu (SAC305) solder alloy shows its great competitiveness on solderability and mechanical properties for the interconnection of high-power LED CSPs. However, reliability problems caused by voids in the SAC305 solder limit its wide application in the high-power LED chip-scale packaging process. Existence of the voids has been considered as one of the major issues causing chip-on-substrate level reliability problems in microelectronic and optoelectronic devices. In this paper, mechanical and thermal properties of SAC305 solder layers with arbitrary voids used in high-power LED CSPs are studied with both finite-element simulations and experiments. The results show that void size and void position within the solder layer are the two most critical issues on the shear strength of interconnection and the chip-on-substrate level thermal distribution in high-power LED CSPs. [ABSTRACT FROM AUTHOR]

Since the introduction of lead-free solder alloys, the impact of voids in solder joints has rapidly gained in importance. Particularly in power electronics, voids in solder joints can reduce their reliability due to less heat dissipation and a significant reduction of the cross-sectional area. While void formation in the printed circuit board (PCB) technology has been the focus of many research projects, the increasing application of molded interconnect devices (MIDs) demands a vivid understanding of void formation and its impact on reliability. This report will show that those processes specific to MID technology do not significantly influence the void formation in SAC305 solder deposits. The processed different roughness levels on Vectra, Vestamid, and FR4 substrate materials show no significant impact on void formation. The surface finish metallization was detected as the most important factor. Especially, the chemical-Sn (iSn) surface finish is inclined to having more voids compared to a nickel–phosphor–gold (NiP-Au) finish. Furthermore, three solder processes were investigated: convection, condensation, and vacuum-condensation soldering. The vacuum-condensation processes significantly reduced the voids in the Sn–3.0Ag–0.5Cu (simplified as SAC305) solder joints of CR0805, MLF20, and switches on all the investigated substrates. An accelerated thermal cycling test of these components according to JESD22-A104D demonstrates no significant effect of the void content of <19% on the solder joints’ reliability. Finally, the result of accelerated thermal cycling shows the possibility to achieve an equivalent lifetime of the solder joints on Vectra in comparison to the FR4 substrate. [ABSTRACT FROM PUBLISHER]

Electromigration (EM) is a growing concern in on-chip interconnects, particularly in the computing and automotive domains. EM can cause wire resistances in a circuit to increase, which may result in circuit performance failure within the lifetime of a product. Classical circuit-level EM models have two drawbacks: first, they do not accurately capture the physics of degradation in modern copper dual-damascene (Cu DD) metallization and second, they fail to model the inherent resilience in a circuit that may allow it to continue to function even after some wires fail. This paper overcomes both limitations, and develops a method to analyze the effect of EM on the resistance of wires in a circuit. For a single wire, our probabilistic analysis encapsulates known realities about Cu DD wires, e.g., that some regions of these wires are more susceptible to EM than others, and that void evolution shows statistical behavior. We develop a new criterion for identifying mortal wires based on this analysis. One part of the criterion incorporates the achievement of steady state and provides a result that is slightly tighter than the traditional Blech criterion, while another part is tied to the lifetime of the system. We apply these ideas to the analysis of on-chip power grids and demonstrate the inherent robustness of these grids that maintains supply integrity under some EM failures. [ABSTRACT FROM PUBLISHER]

In this paper, we investigated GaN-based light-emitting diodes (LEDs) with embedded air voids grown by pulsed growth epitaxial (PGE) method. The void shape can be successfully controlled using the patterned SiO2 AlN/sapphire template and pulsed growth method. By embedding the air voids, we could enhance the 20-mA output power by >61.9%, compared with conventional LED. The improvements could be attributed to the enhanced light extraction efficiency utilizing air voids and improved internal quantum efficiency through PGE method. [ABSTRACT FROM AUTHOR]

We propose a graphene-based photonic crystal fiber (PCF) sensor based on surface plasmon resonance. Graphene helps in prevention of oxidation of the silver layer used as a plasmonic active metal. The birefringent nature of the structure allows one component of the core guided mode to be more sensitive. Further, this structure does not need filling of the voids. The structural parameter of PCF and metal thickness has been optimized. The proposed sensor shows high amplitude sensitivity of 860 RIU-1 and has a resolution as high as 4×10-5 RIU. This reported performance is higher than bimetallic (gold on silver) configuration. [ABSTRACT FROM PUBLISHER]

Electromigration (EM) failure characteristics of patterned NiFe/Cu/NiFe spin-valve (SV) multilayers (MLs) with or without thin Co diffusion barrier inserted at the interface between NiFe and Cu layers have been investigated by applying a constant dc current with different current densities to predict the electrical and magnetic stabilities of metallic SV-based spintronic devices. It was experimentally verified that the Ni-Cu intermixing caused by the EM-induced Cu interdiffusion to the top or bottom NiFe layer plays a dominant role in determining the EM-induced failure characteristics of the NiFe/(Co)/Cu/(Co)/NiFe SV multilayered devices. In addition, it was clearly demonstrated that the interlayer (indirect) exchange coupling field and the magnetic moment of the NiFe/(Co)/Cu/(Co)/NiFe SV-MLs are strongly dependent on the EM-failure induced Ni-Cu intermixing directly relevant to the Cu spacer interdiffusion. The failure mechanism of NiFe/(Co)/Cu/(Co)/NiFe SV multilayered devices showed ldquobimodal failure characteristics.rdquo The critical current density (Jc) for such a bimodal failure mechanism was found to be determined at Jc = 7 times107A/cm2 When J les Jc, the failure was mainly caused by the electrostatic force (or electron wind force) accelerating an interdiffusion through grain boundaries that leads to forming typical EM failures such as voids and hillocks. Whereas, when J > Jc, a melting or a vaporization dominantly accelerated by the Joule heating played more significant role and caused the catastrophic failures. The NiFe/Co/Cu/Co/NiFe SV-MLs showed a much longer mean time-to-failure (t50) than that of NiFe/Cu/NiFe SV-MLs. This experimental result implies that an ultrathin Co insertion layer is effective to improve the EM-induced failure lifetime due to its restraining effects as a diffusion barrier to prevent Cu interdiffusion to both the top and bottom NiFe layers. Furtherm- - ore, this result directly verified that Ni-Cu intermixing is the dominant factor in determining the EM characteristics of the NiFe/Cu/NiFe SV multilayered spintronic devices. [ABSTRACT FROM PUBLISHER]

A coherent methodology was developed for analysing the risk of partial discharge inception in the insulation of high voltage cables containing spherical voids located at the conductor screen interface and fissures located at the insulation screen interface. These two types of insulation defects present the two most important cases from the point of view of insulation integrity in high voltage cable systems. Our approach was based on the notion of sensitivity of dielectric stress to dimensional change of cable insulation and the notion of sensitivity of the size of discharge free defect to the change of electric field intensity. We investigated how modifications of insulation dimensions can affect the risk of discharge in typical defects. The obtained results revealed that so called slim design of HV cables requires that the size of voids is reduced by approximately a third to ensure discharge free operation. The size of fissures must be reduced approximately tenfold in comparison to the permissible size of similar fissures in a standard design to ensure discharge free operation at the interface with accessories. This poses a very high technological demand on new cable system designs of this type. Increasing the size of cable core creates an increased risk of partial discharge, mainly in fissures. Based on the dimensions of a typical 110 kV cable we showed that a reduction of fissure dimensions by approximately a quarter is required for a discharge free operation if the conductor size increases from 1000 mm² to 2000 mm². We have quantified this way the extent to which quality of the insulation extrusion process as well as precision of accessories assembly must improve, in order to assure discharge free operation of cable systems after typical design modifications. [ABSTRACT FROM AUTHOR]

Embedded resistors will potentially allow electronic applications to cost less and perform better. However, it is difficult to fabricate embedded resistors to the correct resistance value, so embedded resistors are often fabricated with a lower value and then trimmed to raise the resistance to the desired value. A computer simulation for the trimming process of an embedded resistor has been developed that has been verified and calibrated against experimental results. A study of embedded resistors containing random voids of varying size has been performed. A new trimming strategy in which the trims are made randomly (rather than conventional L-shaped trims) is proposed and the results of the analysis demonstrate that single-dive trimming combined with random trimming allows higher precision embedded resistors to be obtained than conventional trimming patterns. [ABSTRACT FROM AUTHOR]

The article examines the molecular thermodynamics of water within direct-buried polyethylene power cables. Water, which is almost always present at 100% relative humidity at the typical 1 meter burial depth of the cables, moves very quickly through any polymeric layers. The warmer the cable operates, the wetter the insulation becomes. Temperature cycling, abrupt temperature decreases and loss of voltage on cables cause and enlarge voids, which may start failure on marginal insulation.

A high sensitivity, infrared (IR) microscope operating in the wavelength range 800 to 2500 nm has been applied to a variety of packaging related issues. Applications can be divided into three categories. 1) For flip chip devices the advantage of the IR microscope is that most silicon is effectively transparent at wavelengths greater than 1100 nm. This enable defects such as voids, delamination cracks and corrosion to be investigated while the chip is mounted on the substrate. 2) The IR microscope enables thermal images of devices to be obtained with a temperature resolution of approximately 1 K and spatial resolution of 2-3 μm. 3) The transparency of silicon to IR radiation has proved particularly valuable for characterising micro-electro-mechanical systems (MEMS) devices such as microphones, at various stages of packaging, e.g., after die bonding and wire bonding. [ABSTRACT FROM PUBLISHER]

Failure analyses of 63/37 Sn/Pb solder bumped flip chip assemblies with underfill encapsulant are presented in this study, Emphasis is placed on solder flowed-out, nonuniform underfill and voids, and delaminations. The X-ray, scanning acoustic microscope (SAM), and tomographic acoustic micro imaging (TAMI) techniques are used to analyze the failed samples. Also, cross sections are examined for a better understanding of the failure mechanisms. Furthermore, temperature dependent nonlinear finite element analyses together with fracture mechanics are used to determine the effects of underfill void sizes on the flip chip solder joint reliability [ABSTRACT FROM PUBLISHER]

After being sintered for different times, (Bi,Pb)/sub 2/Sr/sub 2/Ca/sub 2/Cu/sub 3/O/sub 10/ bulk samples were pressed isothermally at 850/spl deg/C under constant pressure of 15 MPa for 1 hour. The samples were examined using SEM, EDS, XRD, and the mass density, critical temperature (T/sub c/) and critical current density (J/sub c/) were measured. As a result of removing voids in the materials under pressure and high temperature. It was found that the mass density significantly increased. In addition to high mass density, grain alignment within the samples was also improved which produced a significant improvement in the J/sub c/. To achieve high J/sub c/, samples require sintering prior to hot-pressing for reasonably long times. [ABSTRACT FROM PUBLISHER]

Scanning electron microscopy, energy dispersive X-ray analysis (including X-ray dot mapping), X-ray diffraction and computer-based image analysis have been used to study non-superconducting secondary phases that evolve during the processing of (Bi,Pb)/sub 2/Sr/sub 2/Ca/sub 2/Cu/sub 3/O/sub x//Ag composite conductors. These investigations have provided new information and insights about specific alkaline earth cuprates (AECs) and lead-rich phases, We can conclusively identify (Ca,Sr)/sub 2/CuO/sub 3/, (Ca,Sr)/sub 14/Cu/sub 24/O/sub 41/ (14/24), and CuO phases, the alkaline earth plumbates, and a (Bi,Pb)-Sr-Ca-Cu-O 3221 phase with a wide range of Pb/Bi ratios. These techniques also help in differentiating voids from secondary phases and alkaline earth plumbates from the lead-rich 3221 phase. [ABSTRACT FROM PUBLISHER]

TaN/IGeTe/Cu devices showed a switching behavior and a considerable increase in the on/off ratio due to GeTe microstructural changes. The Cu diffusion to the GeTe should be the origin of the switching behavior of the prepared devices, which indicates that the conductive bridging characteristics could be obtained even when using a pure GeTe solid electrolyte. The structural characterization suggested that voids are the main diffusion path of metallic bridges and that the electrical resistance of the ON state is dependent on the quantity of voids in the GeTe film. We also found a method for controlling the quantity of voids in a solid electrolyte. [ABSTRACT FROM AUTHOR]

A study of the effect of non-magnetic particles on the magnetic properties of nickel is reported. The presence of inclusions is known to affect the structure sensitive magnetic properties of materials. In this work, two kinds of inclusions, namely, alumina particles and voids were studied and their effects on the magnetic properties were investigated. Powder metallurgy techniques were used to produce nickel compacts with varying amounts of alumina present. While coercivity increased with the volume of inclusions present, initial permeability decreased. Other properties such as remanence and hysteresis loss did not show a significant variation due to their sensitivity to the demagnetizing effects of the inclusions. An attempt has been made in this paper to explain quantitatively the variation in the magnetic properties in terms of the amount of inclusions present. Magnetic property measurements could be a useful non-destructive technique for determining porosity in magnetic materials. [ABSTRACT FROM PUBLISHER]

A critical problem for melt-processed silver-sheathed Bi-2212 tapes is gas release during heat treatment which deforms the sheath ("bubbling") and forms voids in the superconducting core. An overpressure furnace is used to study how the extent of bubbling changes with the total pressure (P/sub tot/). By processing in P/sub tot/ up to 9 atmospheres with constant oxygen partial pressure (pO/sub 2/=1 atm), bubbling in coils is eliminated. The critical current density increases with increasing P/sub tot/. Also, the phase assemblage in overpressure-processed tapes is unchanged compared to conventionally processed tapes. [ABSTRACT FROM PUBLISHER]

Sensor networks have their own distinguishing characteristics that set them apart from other types of networks. Several techniques have been proposed in the literature to address some of the fundamental problems faced by a sensor network design. Most of the proposed techniques attempt to solve one problem in isolation from the others; hence, protocol designers have to face the same common challenges again and again. This, in turn, has a direct impact on the complexity of the protocols and on energy consumption. Instead of using this approach, we propose BEES, a lightweight bioinspired backbone construction protocol, that can help mitigate many of the typical challenges in sensor networks by allowing the development of simpler network protocols. We show how BEES can help mitigate many of the typical challenges inherent to sensor networks including sensor localization, clustering, and data aggregation among others. [ABSTRACT FROM AUTHOR]