253 results on '"Vandooren, A."'
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2. Ultimate Layer Stacking Technology for High Density Sequential 3D Integration
3. Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET
4. Reliability challenges in Forksheet Devices: (Invited Paper)
5. Reliability challenges in Forksheet Devices: (Invited Paper)
6. Low thermal budget PBTI and NBTI reliability solutions for multi-Vth CMOS RMG stacks based on atomic oxygen and hydrogen treatments
7. Low thermal budget PBTI and NBTI reliability solutions for multi-Vth CMOS RMG stacks based on atomic oxygen and hydrogen treatments
8. Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
9. PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch
10. Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
11. PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch
12. Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices
13. Low-temperature atomic and molecular hydrogen anneals for enhanced chemical $\mathbf{SiO}_{2}$ IL quality in low thermal budget RMG stacks
14. Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper
15. Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices
16. Low-temperature atomic and molecular hydrogen anneals for enhanced chemical $\mathbf{SiO}_{2}$ IL quality in low thermal budget RMG stacks
17. Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper
18. Atomic Hydrogen Exposure to Enable High-Quality Low-Temperature SiO2 with Excellent pMOS NBTI Reliability Compatible with 3D Sequential Tier Stacking
19. Enabling UTBB Strained SOI Platform for Co-Integration of Logic and RF: Implant-Induced Strain Relaxation and Comb-Like Device Architecture
20. 3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters
21. Atomic Hydrogen Exposure to Enable High-Quality Low-Temperature SiO2 with Excellent pMOS NBTI Reliability Compatible with 3D Sequential Tier Stacking
22. 3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters
23. Enabling UTBB Strained SOI Platform for Co-Integration of Logic and RF: Implant-Induced Strain Relaxation and Comb-Like Device Architecture
24. LaSiO x - and Al 2 O 3 -Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration.
25. Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
26. Low temperature junctionless device stacking enabled by leading edge sequential 3D integration
27. Low Thermal Budget Dual-Dipole Gate Stacks Engineered for Sufficient BTI Reliability in Novel Integration Schemes
28. BTI Reliability Improvement Strategies in Low Thermal Budget Gate Stacks for 3D Sequential Integration
29. First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
30. Key challenges and opportunities for 3D sequential integration
31. On the Impact of the Gate Metal Work-Function on the Charge Trapping Component of BTI
32. Improved PBTI reliability in junction-less nFET fabricated at low thermal budget for 3D Sequential Integration
33. Semiconductor Technologies for next Generation Mobile Communications
34. Scaling CMOS beyond Si FinFET: an analog/RF perspective
35. Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling
36. Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
37. Low temperature junctionless device stacking enabled by leading edge sequential 3D integration
38. Low Thermal Budget Dual-Dipole Gate Stacks Engineered for Sufficient BTI Reliability in Novel Integration Schemes
39. Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration
40. 3D technologies for analog/RF applications
41. Impact of the Zn diffusion process at the source side of InxGa1−xAs nTFETs on the analog parameters down to 10 K
42. Proton radiation effects on the self-aligned triple gate SOI p-type tunnel FET output characteristic
43. Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: Demonstration of a suitable gate stack for top and bottom tier nMOS
44. Analysis of the transistor efficiency of gas phase Zn diffusion In0.53Ga0.47As nTFETs at different temperatures
45. Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration.
46. Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology.
47. First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
48. BTI Reliability Improvement Strategies in Low Thermal Budget Gate Stacks for 3D Sequential Integration
49. Improved PBTI reliability in junction-less nFET fabricated at low thermal budget for 3D Sequential Integration
50. On the Impact of the Gate Metal Work-Function on the Charge Trapping Component of BTI
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