Search

A highly error resilient mode of the newly standardized 3GPP EVS speech codec is described. Compared to the AMR-WB codec and other conversational codecs, the EVS channel aware mode offers significantly improved error resilience in voice communication over packet-switched networks such as Voice-over-IP (VoIP) and Voice-over-LTE (VoLTE). The error resilience is achieved using a form of in-band forward error correction. Source-controlled coding techniques are used to identify candidate speech frames for bitrate reduction, leaving spare bits for transmission of partial copies of prior frames such that a constant bit rate is maintained. The self-contained partial copies are used to improve the error robustness in case the original primary frame is lost or discarded due to late arrival. Subjective evaluation results from ITU-T P.800 Mean Opinion Score (MOS) tests are provided, showing improved quality under channel impairments as well as negligible impact to clean channel performance.

This paper describes the time-domain bandwidth extension (TBE) framework employed to code wideband and super-wideband speech in the newly standardized 3GPP EVS codec. The TBE algorithm uses a nonlinear harmonic modeling technique that incorporates principles of time-domain envelope-modulated noise mixing. At 13.2 kbps, the super-wideband coding of speech uses as low as 1.55 kbps for encoding the spectral content from 6.4–14.4 kHz. Subjective evaluation results from ITU-T P.800 Mean Opinion Score (MOS) tests are provided, showing significantly improved quality compared to the other standardized SWB codecs under both clean speech and speech with background noise.

This paper presents a low bit-rate MDCT coder, which is adopted as a part of the recently standardized codec for Enhanced Voice Services. To maximize codec performance for NB to SWB input signals for low bit-rates (7.2 to 16.4 kbps), new adaptive bit-allocation and spectrum quantization schemes, which emphasize perceptually important spectrum while efficiently coding full spectrum, was introduced into the low bit-rate MDCT coder. Further, small symbol switched Huffman coding is exploited for reducing the bits consumption for quantizing band energies of the spectrum. Finally, the performance of the coder is illustrated with some listening test results.

In this paper, the latest wideband vocoder standard adopted by the cdma2000 standardization body, 3GPP2, is described. Christened enhanced variable rate codec-wideband (EVRC-WB), the proposed codec encodes wideband speech (16 KHz sampling frequency) at a maximum bit-rate of 8.55 kbit/s. EVRC-WB is based on a split band coding paradigm in which two different coding models are used for the signal components in the low frequency (LF) (0-4 KHz) and the high frequency (HF) (3.5-7 KHz) bands. The coding model used for the former is based on the EVRC-B narrowband (0-4 KHz) codec, modified to encode the LF band signal at a maximum bitrate of 7.75 kbit/s. The HF band coding model is a LPC based coding scheme where the excitation is derived from the coded LF band excitation using non-linear processing. Mean opinion scores from 3GPP2 characterization tests are provided to demonstrate that the EVRC-WB codec (8.55 kbit/s, max.) performs statistically significantly better than the adaptive multirate wideband (12.65 kbit/s, max.).

In this paper, a speech signal estimation framework involving Kalman filters for use as a front-end to the Aurora-2 speech recognition task is presented. Kalman-filter based speech estimation algorithms assume autoregressive (AR) models for the speech and the noise signals. In this paper, the parameters of the AR models are estimated using a expectation-maximization approach. The key to the success of the proposed algorithm is the constraint on the AR model parameters corresponding to the speech signal to belong to a codebook trained on AR parameters obtained from clean speech signals. Aurora-2 noise-robust speech recognition experiments are performed to demonstrate the success of the codebook-constrained Kalman filter in improving speech recognition accuracy in noisy environments. Results with both clean and multi-conditional training are provided to show the improvements in the recognition accuracy compared to the base-line system where no pre-processing is employed.

In this paper, a novel implementation of optimal scalar quantizers using a programmable floating-gate flash analog to digital converter (ADC) is described. The optimal quantization levels for a given signal class are determined according to the Lloyd-Max algorithm. The optimal quantization decision levels are then programmed as the reference voltages for comparators in the floating-gate flash ADC. A test-bench involving the programmable flash ADC and an FPGA interface to a PC is designed. The proposed setup is tested for several signal classes including speech signals and Gaussian random signals. It is demonstrated that significant ADC performance gain, quantified in terms of the signal to noise ratio, may be obtained when optimal scalar quantization is implemented on the floating-gate flash ADC.

In this paper, an FIR adaptive filter implementation using a multiplier-free architecture is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT. The system is implemented on an FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high-speed LMS adaptive filter can be realized employing the proposed architecture.

Distributed arithmetic (DA) is an efficient architecture for implementing finite impulse response (FIR) digital filters. The DA FIR filter calculates the filter output using look up tables (LUTs) instead of multipliers. Thus, a DA based implementation of an FIR filter is highly parameterizable and area efficient. Furthermore, the fundamental building blocks in the DA architecture map well to the architecture of today's field programmable gate arrays (FPGAs). In this paper, we analyze the design of an adaptive FIR filter using the DA architecture on an FPGA. The design trade-offs discussed in detail include throughput, number of logic elements utilized, memory usage, and power consumption estimates.

In this paper, a multiplexed multiplier architecture (MMA) for a field programmable gate array (FPGA) implementation of the least mean square (LMS) adaptive filter is developed and presented. In the proposed architecture, hardware multipliers are reused, i.e. multiplexed in time, for both filtering and adaptation. The number of multipliers may be chosen to achieve certain design trade-offs. The design trade-offs considered in this paper include on-chip area, filter size, maximum filter throughput, and power consumption.