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Computing-in-memory (CIM) is a promising candidate for highly energy-efficient neural networks, alleviating the well-known bottleneck in Von Neumann architecture. MRAM has garnered significant attention in the CIM field, providing advantages in terms of non-volatility, high speed, and endurance. However, most existing MRAM-CIM primarily support low-precision operations, which poses a challenge in fulfilling the requirements of complex neural network models for high inference accuracy. To resolve this dilemma, an in-memory Booth Multiplier is proposed with the aim of enhancing the energy efficiency of neural networks performing multi-bit multiply-and-accumulate (MAC) operations. The MRAM array stores the multiplicand, while the multiplier is encoded by a Booth encoder into corresponding control signals, which perform negation and shift operations, reducing half of the partial products and accelerating the overall processing. Simulation results demonstrate at least a 17.3% improvement in energy efficiency compared to the previous in-SRAM counterpart in 8-bit multiplication. [ABSTRACT FROM AUTHOR]

A magnetic tunneling junction (MTJ) with very low energy barrier, which shows controllable stochastic property, is recently proposed to constitute the probability bit (P-Bit). With the P-Bit, Ising computation, which is a general and powerful computing platform for both conventional and non-conventional problems, is implemented. However, such hardware emulation suffers from the severe intrinsic variations of a stochastic MTJ device. The nonuniform probability switching curves of different stochastic MTJs hinder straightforward expansion of Ising computer to a large P-Bits array for solving more complicated problems. In this work, we propose a novel Ising computer using a single stochastic MTJ device. With the utilization of the time-division multiplexing (TDM) technology, a “Compute–Read–Switch” scheme is proposed, so that the single stochastic MTJ can act as multiple P-Bits during Ising computation. A design guide for the current magnitude and time duration of the “Compute–Read–Switch” scheme is investigated and provided. Furthermore, NOT and XOR logic gates are implemented with our proposal. An accuracy rate as high as 69% for the integer factorization is also achieved, which is comparable with conventional Ising computer. Meanwhile, the TDM Ising computer avoids the calibration process, which is mandatory in the conventional Ising computer. [ABSTRACT FROM AUTHOR]

With the process node further scaling down, the bit cell of magnetic random access memory (MRAM) device suffers from severe failure and reliability problems due to its process variation. In this article, we explored the variability of a promising toggle spin torques MRAM (TST-MRAM) in detail, which achieves ultrafast switching speed and high endurance and is expected to be applied as upper-level caches. Our research is conducted with a 14 nm FinFET design kit, the basic performance of TST-MRAM and different pulse conditions are explored, and then the variation effect of device parameters is discussed and compared in detail as well as the write error rate (WER) under different voltages. The results demonstrate that the variation of access transistors dominates the variability, where the transistor in the spin–orbit torque (SOT) branch has a greater negative impact than the transistor in the spin transfer torque (STT) branch. To further reduce WER, a better structure with diodes of bit cell is proposed. [ABSTRACT FROM AUTHOR]

In this brief, we propose a Two-bits-cell based NAND-Like MRAM device. The structure is composed of several stacking cells sharing the same heavy metal and each cell is composed of two magnetic tunnel junctions (MTJs). Every two stacking MTJs share the same transistor and the demand of three-terminal bit cell for two access transistors is eliminated due to the contribution of NAND-Like structure, thus the area overhead is greatly reduced. For data storage, two steps are required to avoid disturbance in the programming stage after erasing original data, twice as much as data could be stored in comparison with traditional NAND-Like MRAM under the same duration. Thanks to a toggle-like writing scheme adopted in our proposed writing operation, low power consumption, low latency in the programming stage and field-free switching are reached. Based on the Two-bits-cell of our proposed structure, we present a multifunctional sensing circuit which senses two bits data and implements both logic and add operations in memory, which shows a good potential to be applied to the in-memory computing systems. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random access memory (STT-MRAM) offers nonvolatility, good scalability, high speed, and low-power benefits. Multilevel cell (MLC) is an efficient technology to boost the storage density of the STT-MRAM. However, the conventional MLC structure is not suitable for more than 2-b storage due to inefficient multistep read/write operations. In this article, combining the emerging spin-orbit torque (SOT) and STT mechanisms, we propose a novel STT/SOT hybrid triple-level cell (TLC) MRAM cell structure. Corresponding write and read schemes are designed for this hybrid bit-cell to achieve low-cost operations. Unlike the regular stacked TLC, 3-b data can be written in two steps in the proposed cell structure, and be read in parallel with the assistance of SOT. Simulation results show that the proposed structure achieves 32% and 43% savings on write delay and energy consumption, respectively. Monte Carlo statistic simulation results indicate 1.4 × improvement in sensing margin as well. [ABSTRACT FROM AUTHOR]

In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions. [ABSTRACT FROM PUBLISHER]

In this paper, the ac electrical characteristics of metal oxide-based resistive random access memory are investigated based on a developed compact model and the experiment. The voltage–time dilemma phenomenon and the impacts of critical factors on resistive switching speed are addressed. Based on predictions of the model, the small parasitic capacitance, low target high resistance, and large thermal resistance are beneficial to accelerate the resistive switching speed both in SET and RESET processes. The high SET speed and low SET voltage can be achieved by tuning the activation energy of oxygen vacancies. While for the RESET process, the barriers of the release of oxygen ions from electrode and the hopping in resistive switching layer should be turned down simultaneously for high switching speed and low operation voltage. [ABSTRACT FROM PUBLISHER]

In this paper, the fluctuation of random interface traps (RITs) and its interaction with random dopants of 22-nm junctionless FETs (JL-FET) with high-k/metal gate (HKMG) are investigated with 3-D statistical TCAD simulations. The impacts of RIT and random dopant fluctuation (RDF) on the performances of JL-FET are evaluated separately and together. The results show that acceptor-like interface traps mainly affect the drive current, while donor-like interface traps have a significant impact on the subthreshold region. RIT and RDF have different impacts on device performance. Although the influence of RDF is larger than RIT, the impact of RIT cannot be neglected due to their strong correlation. The variation induced by RIT and RDF should be taken into account simultaneously for HKMG JL-FETs. [ABSTRACT FROM PUBLISHER]

Device performance of monolayer MoS2 transistors is investigated by atomistic simulations within the non-equilibrium Green's function formalism. A strong dependence of quantum transport on MoS2 orientation is predicted. To a large extent, the orientation dependence is due to subband transport properties and the atomistic structure along the transport direction. A bandgap is found in the conduction band along armchair direction (AD), which plays a major role for the orientation-dependent transport. At the same time, different atomic arrangements along AD and zigzag direction have different depletion region lengths, which also contribute to the orientation-dependent transport. Orientation dependence of drain current exists in MoS2 FETs having different gate lengths. [ABSTRACT FROM PUBLISHER]