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This work reports the comprehensive study on asymmetric characteristic based on proposed stackable vertical Channel-All-Around (CAA) In-Ga-Zn-O field-effect transistors (IGZO FETs). Sufficient experimental data are analyzed for the reason of performance distinction between normal and reversed source/drain setup. Contact profile has great impacts on device characteristics such as short-channel effects and drain-induced barrier lowering (DIBL) due to different electric filed distributions in the IGZO channel near Schottky barrier. That is mainly caused by different etch process for upper and bottom electrodes, which doesn’t exist in planar structures. Furthermore, a 3-D technology computer-aided design (TCAD) device model is established. Interface defects are applied for slight variation in contact potential to verify the accuracy. Related analysis of contact barriers has been done based on simulation results. What’s more, channel length and etching depth of bottom electrode are also play a role in asymmetric characteristics, which could be applied as a reference to improve devices performance. [ABSTRACT FROM AUTHOR]

The analog resistive switching (RS) characteristics in 2-D polycrystalline (poly-) molybdenum disulfide (MoS2) field-effect transistors (FETs) enable new electronic devices capable of emulating biological synaptic behaviors. In 2-D poly-materials, grain boundary (GB)-induced trap states are of major significance to RS behaviors. However, there is still a lack of appropriate compact models that capture accurate physical mechanisms. Therefore, we developed a surface potential-based compact model, based on the theories of the GB energy barrier and space charge limited current (SCLC). By calibrating to experimental data of MoS2, the physical parameters are extracted, and the model explains the scaling behaviors of channel lengths and grain sizes. Due to the electric-field-induced defect redistribution, the energy barrier modulation at a single-GB (e.g., intersecting GB) quantitatively matches the reported experiments. Moreover, the possible SCLC-based RS behavior is also investigated. Furthermore, we have optimized the set/reset process and simulated the postsynaptic current (PSC) with a tunable potentiation (or depression) process, and then the gate voltage dependence and statistical effects on RS and PSC have been investigated. Thus, this model provides important devices physics insights of 2-D poly-materials and it guides device design, fabrication, and material engineering, to meet the requirements of the future neuromorphic computing application. [ABSTRACT FROM AUTHOR]

Due to structural disorder effects, variable range hopping (VRH) transport via band-tail states has been widely observed in the transition-metal dichalcogenide field-effect transistor (TMD FET). However, this significant mechanism has not been incorporated into existing compact models. In this letter, a continuous physics-based compact model considering VRH in TMD FET is developed. Key parameters are extracted by calibration to experimental molybdenum disulfide FET. The voltage dependent carrier density and temperature dependent current characteristics are physically predicted by utilizing the general percolation theory and generalized Einstein relation. Our model is validated by the good agreement between the simulation and experimental results. Furthermore, the relationship between the disorder effects and circuit-level performances are presented. This letter is significant for material engineering and device optimization of TMD FET. [ABSTRACT FROM AUTHOR]

An improved cut-off frequency model of a modified equivalent circuit of graphene field-effect transistors, which incorporates the additional capacitive effect physically present due to dipole layer between the metal and the graphene, is proposed. The original equivalent circuit is not accurate for a large separation distance dipole layer. Based on the improved equivalent circuit model, a more accurate parameter extraction by two-port analysis is possible, and the cut-off frequency will be more accurate particularly for largely separated dipole layer near the Dirac point. Considering the dipole layer, the equivalent circuit is never investigated before, and the cut-off frequency model shows good agreement with experiments. [ABSTRACT FROM AUTHOR]

In this paper, a surface potential-based gate-leakage current (GLC) model for organic thin-film transistors is proposed. It is found that the Poole–Frenkel emission is the main mechanism of GLC, which can be well described by our model for both accumulation and depletion modes. In addition, the source and drain partitions of the channel leakage current can be well explained based on our model. Furthermore, the dependence of GLC on drain voltage, temperature, and material disorder has been discussed in detail, which yields perfect agreement with the experimental data. [ABSTRACT FROM PUBLISHER]