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This paper presents dual-band 2.4/5-GHz dual-band pHEMT LNAs based on a balanced noise design approach using 0.15 μm pHEMT technology. A dual-band LNA has two input match frequencies without simultaneous noise match at these two frequencies especially when the extrinsic loss caused by the inductor is absent. Noise parameters as a function of frequencies for a dual-band FET LNA based on the balanced noise performance are developed. The fully integrated pHEMT LNA achieves power gain of 18 dB at 2.4 GHz and 12 dB at 5 GHz and noise figure about 3dB at 2.4 GHz and 5 GHz, respectively, at 12.6 mA and 3 V. The pHEMT LNA with a bondwire inductor at input match demonstrates a distinct balanced noise performance.

A high isolation gate-pumped resistive sub-harmonic mixer with a miniature 180° hybrid is demonstrated using 90 nm CMOS process. An in-phase power divider and an out-of-phase Marchand balun form a reduced-size 180° hybrid with shared coupled lines. For a sub-harmonic mixer, the input matches at LO/RF ports of the 180° hybrid are achieved using high/low coupling coefficients of the shared equal-length coupled lines. Moreover, isolations between RF and LO ports are achieved at all frequencies because a Marchand balun maintains balanced signals and a power divider provides in-phase equal magnitude signals at all frequencies. The sub-harmonic mixer achieves a conversion gain around 0-3 dB from 58-67 GHz with 0 dBm LO pumping power. The LO-to-RF isolation is better than 36 dB within the operating bandwidth.

A dual-mode receiver architecture with tens-MHz channel bandwidth at microwave mode and GHz channel bandwidth at millimeter-wave mode is demonstrated in this work with a tunable active filter for RF channel selection at microwave mode using 0.18 μm SiGe BiCMOS technology. A dual conversion is employed to accommodate the wide-channel-bandwidth 60-GHz mode at the first conversion stage and the high-level-modulation 5-GHz mode is merged to the second conversion stage through sharing the 5-GHz switchable Gilbert IQ mixers with the 60-GHz mode. A tunable RF active filter is inserted between the 5-GHz LNA and the second stage mixer to serve as RF channel selection at the 5-GHz mode with the ability of relaxing the stringent linearity requirement imposed by high-level-modulation scheme. 10 dB gain with a 2-GHz channel bandwidth at the 60-GHz mode and 23 dB gain with a 20 MHz channel bandwidth within the 600 MHz tuning range at 5-GHz mode are demonstrated with a low-flicker-noise corner of less than 60 KHz at the 5-GHz mode because of the use of SiGe HBT as the IQ Gilbert mixer cores at the second conversion stage.

A V-band balanced two-stage power amplifier MMICs with Lange couplers is demonstrated using 0.15 µm GaAs pHEMT technology in this paper. A CPWG-MS-CPWG topology with via holes at the transistors as the transition between coplanar waveguide with backside ground (CPWG) and microstrip (MS) is employed for the two-stage amplifier. CPWG is applied to realize the flip-chip transition interface for both input and output ports of the amplifier and interstage MS matching has the advantage of small size. The structure parameters of the CPWG Lange coupler and matching network are designed and optimized for power combining. Finally, a 60-GHz balanced two-stage power amplifier using a CPWG-MS-CPWG structure delivers the small signal gain of 18 dB, OP 1dB of 12 dBm and P sat of 15 dBm.

A 2.4/5.8-GHz dual-band programmable-gain upconverter with a constant IF bandwidth is demonstrated using 0.35-µm SiGe BiCMOS technology. Using a current-mode design approach, the input IF bandwidth remains the same at different gain settings. A dual-band LC current combiner is used at the mixer RF output to combine differential signals to a single-ended one at two bands. Then, a wideband amplifier is cascaded after the dual-band mixer. The demonstrated upconverter achieves maximum gain of −4/−3 dB at 2.4/5.8 GHz, respectively. In addition, four gain steps with 5-dB gain difference between each step are controlled by a two-bit digital circuit. The total current consumption is 26 mA at a 4-V supply.

The effect of layout on silicon SBD in CMOS process is studied in this paper. The size of anode area not only affects the series resistance and SBD junction capacitance but also causes serious parasitic effect from cathode to the p-substrate. Typically, an SBD of a small unit anode has a better cut-off frequency than that of a large unit anode. The cutoff frequency of a small anode Schottky diode is about 700 GHz in a standard 0.18 µm CMOS process. However, a SBD with a small unit anode is prone to the effect of p-substrate to N-well pn junction capacitor. This paper has characterized SBDs of different anode sizes with bottom and side-wall effect of p-substrate to N-well to select an optimal unit-anode area by reducing the substrate effect and providing sufficient f T for high frequency applications.

In this paper, we propose An Android Behavior-Based Malware Detection Method using Machine Learning. We improve an Android application sandbox, Droidbox, by inserting a view-identification automatic trigger program which can click mobile applications in the meaningful order. Taking advantage of Droidbox result, we collect the behavior such as network activities, file read/write and permission as the feature data and use different machine learning algorithms to classify malware and evaluate the performance. We use a large number of malware and normal application samples to prove that our method has high accuracy.

A low-noise low-power direct conversion receiver with a differential RF VGA is demonstrated using 0.18um CMOS technology. A topology that uses a differential inductor load for a differential RF VGA is employed for the single-to-differential conversion. Since the common-mode rejection ratio of a differential variable gain amplifier is increased by the mutual magnetic coupling in a differential inductor load, this work achieves noise floor less than 5 dB covering the 5–6 GHz band. Moreover, the conversion gain is around 50 dB and the total current consumption is 4.75 mA at 1.8 V supply voltage.

This paper demonstrates a millimeter-wave RF-to-DC converter based on Schottky-barrier diodes using 0.18-µm CMOS technology. The Schottky-barrier diode has a cutoff frequency of 400 GHz and a low turn-on voltage of 0.3 V. In the RF-to-DC quadrupler, the difference in turn-on voltages between the Schottky-barrier diode and n-well to p-substrate parasitic pn junction prevents the pn junction from turning on with an effect similar to the Schottky diode clamp in Schottky TTL circuits. The input matching has a better than 10 dB return loss from 50 GHz to 100 GHz. The RF-to-DC quadrupler generates a 3.15 V DC voltage at 84 GHz.

This paper demonstrates a 5.8 GHz low-power, low-flicker-noise I/Q zero-IF receiver in 0.18-um CMOS process. Passive resistive mixers and deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) as the transconductance stage of the IF amplifier are employed to improve the flicker noise problem. The passive mixer is in current mode operation and thus a step-down transformer is used at the LNA output to enhance the current gain. By carefully designing the 4:2 step-down transformer, the conversion gain of the whole zero-IF receiver performs up to 51 dB when LO power is 6 dBm, and the 3-dB bandwidth covers 5.7-6.1 GHz with the current consumption of 4.7 mA at 1.8 V supply. The flicker noise corner is 100 kHz and the noise floor is 6.5 dB. The I/Q amplitude mismatch and phase difference are below 0.05 dB and 2.5°, respectively.

This paper demonstrates a new temperature insensitive bias circuit using a Wilson current mirror for the InGaP/GaAs HBT power amplifier. The Wilson current mirror has a high impedance node for connecting an on/off digital interface and a stable voltage node for injection of feedback signals to achieve a temperature insensitive bias. The fabricated output stage of the power amplifier with the feedback through the Wilson current source shows a stable bias current with current variation from 186 mA to 182 mA for the temperature range from 25 °C to 200 °C. A bias circuit without the feedback through the Wilson current source is also fabricated for comparison and shows a strong bias current variation over temperature.

A fully integrated 0.15-μm AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) divide-by-three injection locked frequency divider (ILFD) with Marchand balun is demonstrated in this paper. The Marchand Balun provides broadband and balanced differential signals at millimeter wave frequencies due to the low loss GaAs semi-insulating substrate. The divide-by-three ILFD performs a locking range from 44 GHz to 47 GHz at the supply voltage of 6 V and the core current consumption is 6.24 mA.

In this paper, the first fully integrated 0.15-µm InAlAs/InGaAs metamorphic high electron mobility transistor (mHEMT) divide-by-three injection locked frequency divider (ILFD) with Marchand balun is demonstrated. The mHEMT technology has 110-GHz cutoff frequency and high tranconductance. Moreover, the Marchand Balun on the semi-insulating GaAs substrate has a low-loss property to provide broadband and balanced differential signals at millimeter wave frequencies. The divide-by-three ILFD performs the locking range from 28.8 GHz to 31.6 GHz under the supply voltage of 6 V and the core current consumption is 17.8 mA.

A Ka-band injection-locked quadrupler MMIC is demonstrated using 0.15-μm pseudomorphic high electron mobility transistor (pHEMT) technology. pHEMT technology is suitable to the millimeter wave quadrupler by using the topology of high-order sub-harmonic injection lock based on a cross-coupled oscillator. Furthermore, thanks to the semi-insulating GaAs substrate, it is easy to implement microwave/millimeter wave passive components to achieve accurate balanced signals. As a result, the measured output power of the quadrupler is 8 dBm for frequency of 30 GHz and the locking bandwidth reaches 300 MHz.

A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 μm CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5–6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.

A low-power low-flicker-noise receiver is demonstrated using 0.18 μm CMOS technology. Vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are used to substitute the mixer switching core and the input stage of subsequent IF VGA. Compared with the conventional CMOS mixer, the excellent flicker noise performance is obtained. As a result, the receiver achieves a 47 dB voltage gain at 2.4-GHz, and the noise figure is 9.6 dB at IF=100 kHz and 5.6 dB for IF>300 kHz. The total current consumption is 4.3 mA at 1.8 V supply voltage.