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This paper analyzes a bridge arm overcurrent accident in a flexible DC converter station. First, the principle of protection division and configuration of converter station is introduced and the principle of overcurrent protection of bridge arm is clarified. Then, the background of the accident is introduced in detail, the fault characteristics of the no-load charging current of the AC energy dissipation device transformer is identified based on the time scale. And the positive and negative low-frequency oscillating currents are superimposed, compared and analyzed. It is concluded that the resonance caused by the impedance matching between the positive and negative converters causes the action of overcurrent protection of the bridge arm, which has certain reference value for analyzing the converter oscillation risk in actual flexible DC projects.

As a kind of adjustable speed motor, PMSM is very sensitive to voltage sags, especially when the driving process is strict with the speed and torque of motor. In this paper, the principle of the variable-frequency drives(VFDs) and mathematical model of PMSM is briefly illustrated. The influence mechanism of voltage sag on variable-frequency adjustable-speed PMSM is analyzed. The simulation model is built by using MATLAB/Simulink, and simulation research on the influence of the basic characteristic of voltage sag on PMSM is conducted. An experimental research platform is developed. Three domestic and foreign brands of variable-frequency drives are selected as the driving equipment of PMSM, and the speed drop and the stator impact current of PMSM driven by different VFDs are researched. The simulation and experimental results show that the smaller the magnitude of voltage sags, the greater the influence on the motor speed. With the increase of the duration of sags, the decrease of the motor speed is in an increasing trend during sags, and the peak value of the stator current is in a downtrend during the voltage recovery. The effects on the operating performance of motor driven by different variable-frequency drives are significantly obvious. The motor speed decreases by a maximum of 30 percent of the rated speed, and the stator impact current exceeds the rated current by three times, which brought great challenges to the operation stability of motor.

Estimation of voltage sags has become increasingly crucial with higher penetration of sensitive devices in the system recently. Single-event indices for voltage sags are essential to form the whole system of estimation. However, it is still difficult to tell how serious a sag is even after the assessment value is got, for there's no reference value to compare with. This paper firstly discussed indices of single-event sags. Then the voltage sag energy was recommended as a typical index irrelevant to the sensitive curves. In order to more intuitively describe the severity degree, a novel classification of severity level was proposed by using the reference values. In detail, CP95, CP75, CP50, and CP25 of the index of numerous sag events were determined as the reference values. To make up for the shortage of the E vs , the events come from not only measured data in grids but also the standard sensitive curves. To determine more reasonable and generalized reference values, the analytic hierarchy process (AHP) was applied to synthesize the reference values by giving each value a weight according to their different significance. Numerical examples show the conciseness and the clarity of the classification method which can provide a more intuitive view of the severity of a single-event sag for customers, device manufactures and the utility.

Cognitive Radio (CR) has been proposed to address the apparent paradox between spectrum scarcity and spectrum underutilization. It requires the use of a reconfigurable architecture to support a wide range of operating modes. In the case of OFDM-based CR, several subcarriers could interfere with licensed (i.e., the primary) users, so there may be a large number of zero-valued input/output points of the IFFT/FFT and the standard FFT algorithms are not efficient in such a situation. In this paper, we discuss how a more appropriate FFT algorithm, transform decomposition, can be mapped onto a reconfigurable baseband processing architecture. Two mapping methods are proposed to meet various user requirements.

New trends in wireless communication systems require multi-standard coexistence and high data rates. In order to meet these requirements, we propose a reconfigurable baseband platform with coarse grained heterogeneous execution units and flexible interconnections, which are controlled by configuration information. In addition, we demonstrate the effectiveness of our approach in three sample implementations, namely RFID, WLAN OFDM and MIMO-OFDM systems. The performance results reveal that this platform is flexible enough to handle various baseband operations with good efficiency and at reasonable resource cost.

An efficient and configurable computational platform is indispensable in order to meet multiple wireless communications standards. We have developed a heterogeneous reconfigurable architecture to support the arithmetic, logic and signal processing functions which are required for transceivers used in standardized wireless local area networks. Each execution unit in this reconfigurable architecture focuses on a certain general operation, so that the combination of them can complete the various algorithms. We demonstrate the effectiveness of our approach through an implementation of the baseband of IEEE 802.11a/b/g standards and evaluate its performance.

With the continued development of RFID technology, a large number of RFID tags are being deployed having different protocols. Hence, a multiprotocol interrogator which can support all of these alternatives has become a design requirement for many systems. While multifunction capability may be implemented using a high performance DSP, CPU or FPGA, those solutions have a large area cost, so an innovative architecture is needed. Starting from an analysis of the algorithms in RFID systems, we propose a reconfigurable architecture for baseband processing to realize the various protocols in the ISO18000 standard. The structure has been specifically designed to support all of the functions needed, so that it performs very efficiently with low area cost. This design has been post-layout simulated with a clock frequency of up to 83 MHz, and the core area is 4 mm2 in a UMC 0.18 mum CMOS process. Compared with other existing processors, the proposed architecture is much more efficient for this application area.

This paper introduces a Gilbert-type active CMOS mixer integrated in 0.18 um process. Radio frequency signals are feed to the input ports of mixer, and then down-converted to IF band of 1 MHz. No inductor is employed in this circuit to reduce the circuit size. The circuit requires a 1.8 V voltage source and consumes only 3.3 mW when in normal mode. With gain increasing strategy, simulation results indicate the active mixer has a conversion gain of 6.2 dB, IIP3 of -4.4 dBm, noise figure of 12.8 dB.It is suitable for low-power frequency translation applications.

A 2.4-GHz wideband fractional-N frequency synthesizer utilizing PFD/DAC structure for Wireless Sensor Network (WSN) Application is presented. In this synthesizer, hybrid of phase/frequency detector and compensated digital-to-analog converter (PFD/DAC) is utilized to achieve phase noise performance as an integer-N synthesizer. The synthesizer is implemented with wide 400 kHz loop bandwidth and 4 us setting time. The chip occupies 1.9 mm2 and consumes 16.4 mA at 1.8-V supply.

This paper presents a class C power amplifier (PA) with high efficiency and linearity , implemented in 0.18 mum CMOS technology. The third harmonic is controlled by Biasing while the second harmonic is limited by employing the differential structure. It delivers a power gain of 19.7 dB at the input power of -12 dBm with power added efficiency (PAE) of 43%. The second and third harmonics are -35.1 dBc and -36.0 dBc. In order to drive a single-ended load, an off-chip balanced-unbalanced (balun) circuit is also designed and analyzed in this paper.

A CMOS polyphase low-IF filter with on-chip frequency control for a 2.4 GHz wireless LAN is presented. Designed in a 1.8 V, 0.18 mum standard CMOS process, this Chebyshev polyphase filter has a 7th order 0.5 dB passband ripple. An on-chip auto frequency control module is designed for the variation of process in order to get the required sensitivity of the filter. This filter consumes 1.74 mW including the on-chip control module and the total chip area is 0.276 mm2.