405 results on '"Wong, H.-S. Philip"'
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2. Barrier Booster for Remote Extension Doping and its DTCO for 1D & 2D FETs
3. Low N-Type Contact Resistance to Carbon Nanotubes in Highly Scaled Contacts through Dielectric Doping
4. Multi-gate FeFET Discriminates Spatiotemporal Pulse Sequences for Dendrocentric Learning
5. Gain Cell Memory on Logic Platform – Device Guidelines for Oxide Semiconductor Transistor Materials Development
6. Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel
7. High-Endurance MoS2 FeFET with Operating Voltage Fess Than IV for eNVM in Scaled CMOS Technologies
8. pMOSFET with CVD-grown 2D semiconductor channel enabled by ultra-thin and fab-compatible spacer doping
9. Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties
10. First Demonstration of Top-Gated ITO Transistors: Effect of Channel Passivation
11. Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS
12. Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor
13. Antimony Semimetal Contact with Enhanced Thermal Stability for High Performance 2D Electronics
14. Sub-200 Ω·µm Alloyed Contacts to Synthetic Monolayer MoS2
15. Understanding Interface-Controlled Resistance Drift in Superlattice Phase Change Memory.
16. Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors.
17. Improved Contacts to Synthetic Monolayer MoS2 – A Statistical Study
18. Impact of Metal Hybridization on Contact Resistance and Leakage Current of Carbon Nanotube Transistors.
19. Bandgap Extraction at 10 K to Enable Leakage Control in Carbon Nanotube MOSFETs.
20. Pinning-Free Edge Contact Monolayer MoS2 FET
21. Electro-Thermal Confinement Enables Improved Superlattice Phase Change Memory.
22. SAPIENS: A 64-kb RRAM-Based Non-Volatile Associative Memory for One-Shot Learning and Inference at the Edge.
23. Reduced HfO₂ Resistive Memory Variability by Inserting a Thin SnO₂ as Oxygen Stopping Layer.
24. A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping for Energy-Efficient RRAM-Based In-Memory Computing
25. High On-Current 2D nFET of 390 μA/μm at VDS = 1V using Monolayer CVD MoS2 without Intentional Doping
26. 33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models
27. Monolithic Heterogeneous Integration of BEOL Power Gating Transistors of Carbon Nanotube Networks with FEOL Si Ring Oscillator Circuits
28. RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays.
29. IC Technology – What Will the Next Node Offer Us?
30. Vertical Sidewall MoS2 Growth and Transistors
31. First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate
32. 14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques
33. Error-Resilient Analog Image Storage and Compression with Analog-Valued RRAM Arrays: An Adaptive Joint Source-Channel Coding Approach
34. First Principles Study of Memory Selectors using Heterojunctions of 2D Layered Materials
35. Integrating Graphene into Future Generations of Interconnect Wires
36. Bidirectional Analog Conductance Modulation for RRAM-Based Neural Networks.
37. Two-Fold Reduction of Switching Current Density in Phase Change Memory Using Bi₂Te₃ Thermoelectric Interfacial Layer.
38. Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector–MTJ Cooptimization.
39. A Density Metric for Semiconductor Technology [Point of View].
40. Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part I: Accurate and Computationally Efficient Modeling.
41. Next-Generation Ultrahigh-Density 3-D Vertical Resistive Switching Memory (VRSM)—Part II: Design Guidelines for Device, Array, and Architecture.
42. Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology.
43. Monolithic 3-D Integration.
44. TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration Using Carbon Nanotube FETs
45. Selector Requirements for Tera-Bit Ultra-High-Density 3D Vertical RRAM
46. Energy-Efficient Phase Change Memory Programming by Nanosecond Pulses
47. Low Power Nanoscale Switching of VO2using Carbon Nanotube Heaters
48. The End of the Road for 2D Scaling of Silicon CMOS and the Future of Device Technology
49. Coming Up N3XT, After 2D Scaling of Si CMOS
50. Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study
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