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Resistance drift in phase change memory (PCM) reduces the accuracy of analog computing applications such as neural network inference. Recently, PCMs based on superlattice (SL) phase change layers have shown low resistance drift, however the origin of this low drift remains unexplored. Here, we uncover that resistance drift in SL-PCM based on alternating layers of Sb2Te3 and Ge2Sb2Te5 (GST) is controlled by the number of SL interfaces as well as the degree of SL intermixing. Temperature-dependent measurements reveal smaller and more stable activation energy upon annealing (thus suppressed structural relaxation) in our SL-PCM vs. control GST devices, accounting for the low resistance drift. By controlling SL interfaces, we achieve low resistance drift coefficient ${v} < 0.01$ in these SL-PCMs, maintained after extensive cycling and at various read voltages and intervals - showing robustness required for analog computing with PCM. [ABSTRACT FROM AUTHOR]

Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > $2\times $ error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions. [ABSTRACT FROM AUTHOR]

Carbon nanotube field effect transistors (CNFETs) have potential applications in future logic technology as they display good electrostatic control and excellent transport properties. However, contact resistance and leakage currents could limit scaling of CNFETs. Non-equilibrium Green’s function (NEGF) simulation investigates that coupling between contact metal and CNT impacts both contact resistance and leakage current. The physical mechanisms underlying the effects are analyzed. A model with calibrated metal coupling strength from experimental data projects ION-IOFF design space to understand the trade-off between shrinking contact and extension lengths. For CNT with diameter of 1 nm, both contact and extension lengths greater than 8 nm are a good compromise between ION and IOFF for digital logic in advanced technology nodes. [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) transistors exemplify the fundamental tradeoff between desirable high mobility and undesirable leakage current due to the small effective mass and bandgap. To understand leakage current limits in high-speed CNT transistors, electrical bandgaps are extracted on 12 single-CNT top-gate MOSFETs from the energy gap between thermionic emission and band-to-band tunneling (BTBT) at 10 K. At 300 K the minimum IOFF at 0.5 V VDS is analyzed as a function of bandgap between 0.96 eV and 0.43 eV with IOFF-MINfrom 0.2 pA/CNT to 15 nA/CNT. NEGF simulation validates the bandgap extraction methodology and reproduces the experimental MOSFET IOFF-MIN data. A TCAD model calibrated to this work’s leakage data projects the accessible ION-IOFF design space bounded by CNT bandgap, indicating EG > 0.65 eV (dCNT < 1.3 nm) is needed to achieve 100 nA/ $\mu \text{m}$ at 0.5 V VDD and 250 CNT/ $\mu \text{m}$ for channel length above 20 nm. An EG of 1.06 eV (dCNT = 0.8 nm) can deliver $2750\times $ tunable range of IOFF by adjusting VT, which exceeds the $400\times $ tunable range of IOFF used in Si CMOS platform technologies. [ABSTRACT FROM AUTHOR]

Large switching current density and resistance drift remain challenges for phase change memory (PCM) in data storage and neuromorphic computing applications. Here, we address these by electro-thermal and structural confinement in a GeTe/Sb2Te3 superlattice PCM (SL-PCM) with thermally-induced phase change, while observing scalability with bottom electrode diameter. We demonstrate ~ $\text{8-10}\times $ reduction of reset current density $({J}_{\text {reset}})$ and ~ $\text{25-30}\times $ reduction of power $({P}_{\text {reset}})$ in our mushroom cell SL-PCM compared to control Ge2Sb2Te5 (GST) PCM with the same device structure. The SL-PCM devices also exhibit multi-level states with $\sim 10\times $ lower resistance drift compared to control GST PCM. Material characterization and electro-thermal simulations confirm the role of heat confinement in SL-PCM, paving the way towards low-power, high-density memory and data storage. [ABSTRACT FROM AUTHOR]

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning with Stanford Associative memory for Programmable, Integrated Edge iNtelligence via life-long learning and Search (SAPIENS), a resistive random access memory (RRAM)-based non-volatile associative memory (AM) chip that serves as the backend for memory-augmented neural networks (MANNs). The 64-kb fully integrated RRAM-CMOS AM chip performs long-term feature embedding and retrieval, demonstrated on a 32-way one-shot learning task on the Omniglot dataset. Using only one example per class for 32 unseen classes during on-chip learning, SAPIENS achieves 79% measured inference accuracy on Omniglot, comparable to edge software model accuracy using five-level quantization (82%). It achieves an energy efficiency of 118 GOPS/W at 200 MHz for in-memory L1 distance computation and prediction. Multi-bank measurements on the same chip show that increasing the capacity from three banks (24 kb) to eight banks (64 kb) improves the chip accuracy from 73.5% to 79%, while minimizing the accuracy excursion due to bank-to-bank variability. [ABSTRACT FROM AUTHOR]

One of the major roadblocks for filamentary type resistive random access memory is variations in both the write voltage and the read resistance. The variation is inevitable because of the stochastic nature of oxygen ion movement inside the metal oxide. In this letter, we show that by inserting a thin SnO2 layer within the HfO2 switching layer, these variations can be significantly reduced. The TiN/HfO2/SnO2/HfO2/Pt material stack achieves ~ 10 times smaller standard deviation for the high resistance state($>100\text{k}\Omega $) cycle to cycle distribution compared with the control group without the SnO2 layer. The tight high resistance state distribution retained after 107 pulse cycling. Incremental RESET pulse measurement indicates that the thin SnO2 acts as an oxygen stopping layer and thus explains the origin of reduced variability. The concept of an oxygen stopping layer is promising for reducing variability for resistive memory. [ABSTRACT FROM AUTHOR]

HfO2-based resistive RAM (RRAM) is an emerging nonvolatile memory technology that has recently been shown capable of storing multiple bits-per-cell. The energy/delay costs of an RRAM write operation are dependent on the number of pulses required for RRAM programming. The pulse count is often large when existing programming approaches are used for multiple bits-per-cell RRAM, especially when resistance ranges are allocated to account for retention. We present a new technique, Range-Dependent Adaptive Resistance (RADAR) Tuning, for fast and energy-efficient programming of multiple bits-per-cell RRAM arrays, using a combination of coarse- and fine-grained RRAM resistance tuning. Experimental data are collected on 16k cells from two 1Megacell (1M physical cells) 1T1R HfO2-based RRAM arrays fabricated in a 130-nm CMOS process. RADAR reduces the programming pulse count by 2.4X (for both uncycled cells and cells that have undergone 8k cycles) on average over existing programming techniques tested on the same RRAM arrays, with the same bit error rate targets. [ABSTRACT FROM AUTHOR]

Increasing computation demand of machine learning (ML) applications (recommender system, image classification, speech recognition, and so on) calls for the development of specialized hardware for ML and neuromorphic computing. New memories, such as resistive random access memory (RRAM), can be used to store weights of neural networks and to accelerate matrix multiplication, the dominant operation in neural networks. One of the key challenges for RRAM-based neural networks is to achieve bidirectional analog conductance modulation for online training. This article provides a programming scheme (SRA: small RESET voltage amplitude and appropriate SET voltage) to achieve bidirectional analog conductance modulation of RRAM devices. We find that both abrupt and gradual SET can be obtained for the same device. The controlling parameters for modulating the gradual SET behavior are the SET voltage and the local device temperature. We suggest that the filament morphology before SET may be the key to understanding this phenomenon; gradual SET is obtained when the filaments have a single-layer gap in the RESET state, and abrupt SET is obtained when the filaments have a multilayer gap in the RESET state. [ABSTRACT FROM AUTHOR]

High switching current density has been a key bottleneck for phase change memory (PCM) technology. Here, we demonstrate interfacial thermoelectric heating (TEH) as a promising way of tackling this challenge. We use TEH induced by a thin Bi2Te3 interfacial layer to demonstrate $\sim 2\times $ reduction of reset current density (${J} _{\text{reset}}$) and power (${P} _{\text{reset}}$) compared to control PCM devices based on Ge2Sb2Te5 (GST). Measurements of polarity-dependent reset current and power in well-cycled devices reveal the strong TEH caused by the Bi2Te3 interfacial layer. The TEH origin of ${J} _{\text{reset}}$ reduction is further confirmed by electro-thermal simulations. Such TEH-engineered PCM devices are scalable with the bottom electrode diameter and thus could be promising for high density data storage applications. [ABSTRACT FROM AUTHOR]

To increase the density of magnetoresistive random access memory (MRAM) beyond the 1T1MTJ MRAM cell in use today, the design space for 1S1MTJ MRAM array is analyzed by cooptimizing both selectors and MTJs. Current low-resistance MTJs for 1T1MTJ MRAM are not suitable for 1S1MTJ MRAM. Threshold-type selectors would induce a strong read disturb on the MTJ due to the snapback voltage (VTH – VHOLD) when the selector is turned on. Also, exponential-type selectors would degrade the read margin (RM) due to its large ON-state resistance. When using existing selectors to achieve a 1-M-bit 1S1MTJ array, it is necessary to adjust the product of resistance and area (RA) and the diameter of the MTJ. An MTJ with the RA = 15 Ω ⋅ μm2 and the diameter = 50 nm can meet the criterion of RM > 10% for both exponential-type selectors (exponential slope = 300–500 mV/decade with the current density ~ 1 MA/cm2) and threshold-type selectors (VTH – VHOLD ~250 mV). A design space accommodating a selector variation of around 1% can be found for MTJs with tunnel magnetoresistance ratio (TMR) < 250%. With an increased TMR of 250%–350% of the MTJ, the tolerance of variations for exponential-type selectors and threshold-type selectors can be improved to 2% and 4%, respectively. This provides a chance for the 1S1MTJ MRAM with existing selectors. [ABSTRACT FROM AUTHOR]

Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances in semiconductor device technologies enable system-level benefits. The proposed metric can be used to gauge advances in future generations of semi-conductor technologies in a holistic way, by accounting for the progress in logic, memory, and packaging/integration technologies simultaneously. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RSM) shows potentials for high-capacity storage because of its simple cell structure, small footprint, and good scalability. This two-part article discusses how to implement ultrahigh-density (~terabits) storage with RSM covering design considerations from device to memory array architecture. In Part I of this two-part article, an accurate and computationally efficient model is developed to study 3-D vertical RSM (VRSM). In this article, we use 3-D VRSM with a hexagon-patterned pillar layout (3-D hexagon VRSM) as an example to elaborate our approach. Using the parasitic resistance extracted from physics-based 2-D field solver as the reference, we develop a lumped resistor network for SPICE simulation to accurately capture all leakage currents of the array. This full resistor network is further simplified to a reduced network to achieve high computational efficiency and maintain the full network accuracy (with a relative error <2%). Without this simplification, practical memory array sizes cannot be simulated efficiently. The interplay between the memory cell resistance values and selector nonlinearity (NL) on the maximum array size and the write/read margins under the worst case scenarios is discussed. Large memory cell resistance (low-resistance states ≥100 k) with enough NL (~103) from the selector is recommended for successful write/read operations in a single 3-D hexagonal VRSM array of megabit scale. [ABSTRACT FROM AUTHOR]

Using the reduced resistor network developed in Part I of this two-part article, we present practical design guidelines from device to architecture levels to achieve ultrahigh-density 3-D vertical resistive switching memory (VRSM). We first design both hexagon and comb arrays using 7-nm FinFET as pillar driving transistors (pillar drivers). Small-footprint pillar drivers are necessary for a high pillar areal density competitive to 3-D NAND. We then organize the arrays into an architecture using the compact staircase and highly conductive wordplane connection (WPC) to maximize array efficiency and chip density. We investigate the memory and selector requirements, tolerance of parasitic resistances, latency, and energy consumption for both hexagon and comb architectures. The results indicate that the hexagon array with large low-resistance state (LRS) and nonlinearity (NL) is required for ultradense 3-D VRSM. Compared to the comb array, the hexagon array benefits from a continuous WP pattern and yields a better tolerance of parasitic resistances and a smaller latency. The energy consumptions of both architectures are similar. Compared to the most advanced 3-D NAND, 3-D VRSM has higher chip density and shows better potential for future ultradense storage. [ABSTRACT FROM AUTHOR]

For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 106, a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL). [ABSTRACT FROM AUTHOR]

The demands of future applications in computing (from self-driving cars to bioinformatics) overwhelm the projected capabilities of current electronic systems. The need to process unprecedented amounts of loosely structured data is driving the push for ultradense and fine-grained integration of traditionally off-chip components (e.g., sensors, memories) with energy-efficient computation units—all within a single chip. Monolithic 3-D integration is a leading approach for building such future systems, as it naturally enables ultradense connectivity between various heterogeneous technologies inside a single chip. This article discusses exciting recent progress toward realizing monolithic 3-D systems and elucidates key benefits that these new systems offer. Monolithic 3-D integration promises to enable the next wave of gains in performance (both energy and speed) for coming generations of applications as well as provides the means for developing rich additional functionalities such as sensing-immersed-in-computation that lie beyond the scope of traditional computing today. [ABSTRACT FROM AUTHOR]