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This article presents a third-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which exploits a hybrid error control topology to increase the order of the noise-transfer function (NTF). This scheme is a hybrid of two NS stages, namely, a cascaded integrator feed-forward (CIFF) and an error feedback (EF). This EF-CIFF structure contributes a more effective NS capability and enhances the robustness of the high-order NTF. An improved dither-based digital calibration is developed to mitigate the harmonic distortion caused by the capacitor mismatch. Due to the usage of an averaging filter, this calibration greatly reduces the interference of quantization noise on mismatch extraction while only needing a minimum modification in a standard SAR Topology. Hence, our scheme is simple and inherently robust to the process, voltage, and temperature variation. Based on an 8-bit SAR, our prototype is fabricated in a 130-nm CMOS process. It consumes a 96- $\mu \text{W}$ power when operating at a 2-MS/s sampling frequency with a 1.2-V supply. The proposed NS-SAR yields a peak Schreier figure of merit of 170.7 dB with a signal-to-noise-and-distortion ratio (SNDR) of 79.57 dB at an oversampling ratio of 8. [ABSTRACT FROM AUTHOR]

This article presents a 12-bit column-parallel two-step single-slope analog-to-digital converter (SS ADC). With the merging of analog memory capacitor and input sampling capacitor, the proposed two-step SS ADC realizes simultaneously residue storage and zero-cross detection. The fixed decision point guarantees a static comparator offset. A constant input common-mode level resistor ramp generator, which exploits a current-mode R-2R digital-to-analog converter (DAC) and a variable feedback R-string DAC, is developed to enhance ADC linearity limited by finite common-mode rejection ratio (CMRR) of the operational amplifier. Using a bottom-up foreground self-calibration, harmonic distortion caused by both parasitic capacitor and resistor mismatch is mitigated. This prototype is fabricated using a 130-nm CMOS process. The proposed two-step SS ADC consumes 62- $\mu \text{W}$ power when operating at a 100-KS/s sampling frequency and yields a peak spurious-free dynamic range (SFDR) of 76.47 dB with a signal-to-noise-and-distortion ratio (SNDR) of 60.78 dB. The measured differential nonlinearity (DNL) and the integral nonlinearity (INL) are 0.83/−1 and 4.78/−3.31 LSB, respectively. [ABSTRACT FROM AUTHOR]

Focal stack images (FoSIs) are a set of 2D images that captured one scene with serial focal depths. The redundancies of FoSIs mainly come from gradual focused depths changes rather than motion of objects. Conventional coding schemes cannot fully exploit such redundancies, leading to coding inefficiency. In this paper, we propose a new Gaussian-Wiener representation to model the gradual focused depths changes among FoSIs. In the representation, image degradation-restoration relations are utilized to describe the focus-defocus changing characteristics of FoSIs. Based on this representation, we propose a new hierarchical coding scheme for fully exploiting the inter-frame redundancies of FoSIs. In the scheme, a Gaussian-Wiener representation based inter prediction (GWR-IP) is presented by embedding Gaussian convolution and Wiener deconvolution into normal video encoder. Block-wise focus-defocus changing of FoSIs can be predicted in bi-directional manner by solving optimization problem. For higher coding efficiency, a Gaussian-Wiener representation based hierarchical prediction structure (GWR-HPS) is also designed and applied in the coding scheme. The proposed coding scheme is performed on 10 test sequences, including 5 synthetic scenes and 5 realistic scenes. Experimental results show that proposed coding scheme can obtain 2.640 dB PSNR gains and 51.830% bitrate savings on average of all test sequences in Low Delay P configuration, 2.123 dB PSNR gains and 43.975% bitrate savings in Low Delay B configuration, and 1.044 dB PSNR gains and 26.078% bitrate savings in Random Access configuration. Particularly, it achieves up to 65.544% bit rate savings and 3.901 dB PSNR increments for test sequence I09 in Low Delay P configuration. Furthermore, ablation test demonstrates that Gaussian representation contributes more on coding performance than Wiener representation and GWR-HPS. [ABSTRACT FROM AUTHOR]

This article presents a low-power code-recombination (CR) analog-to-digital converter (ADC) with generic feature extraction for wearable electrocardiogram (ECG) sensors in wireless body sensor network (WBSN) applications. The CR ADC features a search forward procedure (SFP) and a search backward procedure (SBP) to hunt for part of the quantization steps cutting down bitcycle and power consumption. Also, CR ADC outputs a digital stream named $K$ data served as a compressed feature. A prototyped chip including a proposed ADC is fabricated in a 0.13- $\mu \text{m}$ CMOS process. With a 0.6-V supply voltage and a 10-kS/s sampling rate, the measured signal-to-noise-distortion range (SNDR) and spurious-free dynamic range (SFDR) are 58.34 and 70.2 dB, respectively. The ADC consumes only 40-nW power when input residue is within the prediction range defined by ADC’s resolution and the reference voltage, achieving a figure-of-merit (FoM) of 6.2 fJ/conversion-step. The data $K$ occupy 2/5 of the raw data and are conducted to categorize cardiovascular diseases illustrating at least 96% accuracy. [ABSTRACT FROM AUTHOR]

All-CMOS monolithic microdisplay technologies have been attracting attention due to their direct integration of light-emitting pixel arrays and driving circuits on a single silicon substrate. Improvements to optical power efficiency have been a hot spot for all-silicon microdisplay technologies. MOS-like gate-control structure avalanche-mode light-emitting diodes (AMLEDs) that employ hot-carrier electroluminescence to produce light emission are used to enhance the optical power efficiency of pixel units. A semi-active matrix mode is used to reduce the power consumption of driver circuits. A 100 × 100 pixel array with an all-CMOS monolithic microdisplay system is demonstrated using standard 0.18 μm CMOS technology. The optical emission power and the breakdown voltage of the proposed AMLEDs are increased by 139.2% and reduced by more than 67%, respectively. The optical-power efficiency is 5.98 × 10−7 which is comparable to the best reported so far in all-CMOS monolithic microdisplay chip. With its significant optical-power efficiency, the proposed microdisplay technology has broad application prospects in near-to-eye display and head mounted displays (HMDs). [ABSTRACT FROM AUTHOR]

This brief presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with two passive integrators. Due to the separation of the preamplifier, these two integrators become independent of each other and the size of the second integrator can be reduced. The NS SAR also realizes the zeros optimization of the noise transfer function (NTF). The analysis shows the NS performance of the proposed ADC is insensitive to the gain variation of the multipath comparator. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-code 4-bit MSBs are implemented with data weighted averaging (DWA) technique. The overall architecture is simple and robust, which only requires minor modifications to the standard SAR ADC. A prototype 9-bit NS-SAR ADC is designed and simulated in a 130-nm CMOS process. It consumes $59.9~\mu \text{W}$ of power when operating at 2-MS/s sampling frequency. The proposed ADC achieves peak Schreier figure of merits (FoMs) of 171.9 dB with 78.69-dB signal-to-noise-and-distortion ratio (SNDR) at an oversampling ratio (OSR) of 8. [ABSTRACT FROM AUTHOR]